makefile changes/split | add scripts
This commit is contained in:
abejgonzalez
parent
49ab106b9e
commit
82273107c1
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@ -0,0 +1,13 @@
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--langdef=scala
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--langmap=scala:.scala
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*class[ \t]+([a-zA-Z0-9_]+)/\4/c,classes/
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*object[ \t]+([a-zA-Z0-9_]+)/\4/o,objects/
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*((abstract|final|sealed|implicit|lazy)[ \t ]*)*case class[ \t ]+([a-zA-Z0-9_]+)/\6/C,case classes/
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*case object[ \t]+([a-zA-Z0-9_]+)/\4/O,case objects/
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy)[ \t]*)*(private[^ ]*|protected)?[ \t]*trait[ \t]+([a-zA-Z0-9_]+)/\4/t,traits/
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--regex-scala=/^[ \t]*type[ \t]+([a-zA-Z0-9_]+)/\1/T,types/
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*(\[[a-z]*\])*|protected)[ \t]*)*def[ \t]+([a-zA-Z0-9_]+)/\4/m,methods/
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*val[ \t]+([a-zA-Z0-9_]+)/\3/V,values/
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--regex-scala=/^[ \t]*((abstract|final|sealed|implicit|lazy|override|private[^ ]*|protected)[ \t]*)*var[ \t]+([a-zA-Z0-9_]+)/\3/v,variables/
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--regex-scala=/^[ \t]*package[ \t]+([a-zA-Z0-9_.]+)/\1/p,packages/
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@ -0,0 +1 @@
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*/target
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@ -3,10 +3,11 @@ bootrom
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target
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*.jar
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*.stamp
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/vsim
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/verisim/generated-src*
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/verisim/simulator-*
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/verisim/verilator
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/sims/vsim
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/sims/verisim
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simv*
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*.vcd
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*.swp
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.idea
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.DS_Store
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tags
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105
Makefrag
105
Makefrag
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@ -1,50 +1,38 @@
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ROCKETCHIP_DIR=$(base_dir)/generators/rocket-chip
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TESTCHIP_DIR = $(base_dir)/generators/testchipip
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SCALA_VERSION=2.12.4
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SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
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SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
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#########################################################################################
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# set default shell for make
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#########################################################################################
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SHELL=/bin/bash
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#########################################################################################
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# variables to get all *.scala files
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#########################################################################################
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lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)
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PACKAGES=rocket-chip testchipip
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SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
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#########################################################################################
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# rocket and testchipip classes
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#########################################################################################
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ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
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TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes"
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#########################################################################################
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# jar creation variables and rules
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#########################################################################################
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FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
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# this should match whatever the commonSettings version is in build.sbt
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BARSTOOLS_VER=1.0
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TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar
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MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar
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$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
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$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
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mkdir -p $(dir $@)
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cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
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touch $@
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build_dir=$(sim_dir)/generated-src
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CHISEL_ARGS ?=
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long_name=$(PROJECT).$(MODEL).$(CONFIG)
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FIRRTL_FILE ?=$(build_dir)/$(long_name).fir
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ANNO_FILE ?=$(build_dir)/$(long_name).anno.json
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VERILOG_FILE ?=$(build_dir)/$(long_name).top.v
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HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v
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SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v
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SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf
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sim_dotf ?= $(build_dir)/sim_files.f
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REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
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# This should match whatever the commonSettings version is in build.sbt
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BARSTOOLS_VER=1.0
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TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar
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MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar
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TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR)
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MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR)
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$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala)
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cd $(base_dir) && $(SBT) "tapeout/assembly"
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@ -54,13 +42,32 @@ $(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macr
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.PHONY: jars
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jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
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#########################################################################################
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# tapeout and macrocompiler commands
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#########################################################################################
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TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR)
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MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR)
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#########################################################################################
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# create simulation args file rule
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#########################################################################################
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$(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
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cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
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#########################################################################################
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# create firrtl file rule and variables
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#########################################################################################
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CHISEL_ARGS ?=
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$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
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mkdir -p $(build_dir)
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cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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#########################################################################################
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# create verilog files rules and variables
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#########################################################################################
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REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
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$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
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$(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir)
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@ -71,6 +78,30 @@ $(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
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$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR)
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$(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops
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#########################################################################################
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# run assembly/benchmarks rules
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#########################################################################################
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$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
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mkdir -p $(output_dir)
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ln -sf $< $@
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$(output_dir)/%.run: $(output_dir)/% $(sim)
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$(sim) +max-cycles=$(timeout_cycles) $< && touch $@
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$(output_dir)/%.out: $(output_dir)/% $(sim)
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$(sim) +verbose +max-cycles=$(timeout_cycles) $< 3>&1 1>&2 2>&3 | spike-dasm > $@
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#########################################################################################
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# include build/project specific makefrags made from the generator
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#########################################################################################
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ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
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-include $(build_dir)/$(long_name).d
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endif
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#########################################################################################
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# default regression tests variables and rules
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# TODO: Remove in favor of each project having its own regression tests?
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#########################################################################################
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regression-tests = \
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rv64ud-v-fcvt \
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rv64ud-p-fdiv \
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@ -98,12 +129,14 @@ regression-tests = \
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rv64um-v-mulh \
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rv64si-p-dirty
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output_dir=$(sim_dir)/output
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$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
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mkdir -p $(output_dir)
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ln -sf $< $@
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.PHONY: run-regression-tests run-regression-tests-fast run-regression-tests-debug
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run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
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run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
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run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
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#########################################################################################
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# general jar cleanup rule
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#########################################################################################
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.PHONY: clean-scala
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clean-scala:
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rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
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@ -0,0 +1,79 @@
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#########################################################################################
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# makefile variables shared across multiple makefiles
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#########################################################################################
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#########################################################################################
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# default variables to invoke the generator
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# descriptions:
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# PROJECT = the scala package to find the MODEL in
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# MODEL = the top level module of the project
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# CONFIG = the configuration class to give the parameters for the project
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# CFG_PROJECT = the scala package to find the CONFIG class
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# TB = TODO
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# TOP = TODO
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#########################################################################################
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PROJECT ?= example
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MODEL ?= TestHarness
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CONFIG ?= DefaultExampleConfig
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CFG_PROJECT ?= $(PROJECT)
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TB ?= TestDriver
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TOP ?= ExampleTop
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#########################################################################################
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# path to rocket-chip and testchipip
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#########################################################################################
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ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip
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TESTCHIP_DIR = $(base_dir)/generators/testchipip
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#########################################################################################
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# names of various files needed to compile and run things
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#########################################################################################
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long_name = $(PROJECT).$(MODEL).$(CONFIG)
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FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
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ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
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VERILOG_FILE ?= $(build_dir)/$(long_name).top.v
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HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
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SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v
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SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
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sim_dotf ?= $(build_dir)/sim_files.f
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#########################################################################################
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# default sbt launch command
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#########################################################################################
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SCALA_VERSION=2.12.4
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SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
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SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION)
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#########################################################################################
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# output directory for tests
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#########################################################################################
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output_dir=$(sim_dir)/output
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#########################################################################################
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# build output directory for compilation
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#########################################################################################
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build_dir=$(sim_dir)/generated-src
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#########################################################################################
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# vsrcs needed to run projects
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#########################################################################################
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rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
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#########################################################################################
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# sources needed to run simulators
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#########################################################################################
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sim_blackboxes = \
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$(build_dir)/firrtl_black_box_resource_files.f
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sim_vsrcs = \
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$(VERILOG_FILE) \
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$(HARNESS_FILE) \
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$(SMEMS_FILE)
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#########################################################################################
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# assembly/benchmark variables
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#########################################################################################
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timeout_cycles = 10000000
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bmark_timeout_cycles = 100000000
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#!/usr/bin/env bash
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# run this script in the main rebar directory to generate ctags for all relevant repos
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# note: this requires exuberant-ctags
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# tested with: Exuberant Ctags 5.8
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# instructions:
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# cd /path/to/rebar/
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# ./scripts/gen-tags.sh
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#
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# input:
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# * nothing
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#
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# output:
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# * tags file in the directory that this was called in
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# ctags wrapper
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ctags -R --exclude=@.ctagsignore --links=no
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@ -1,41 +1,43 @@
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#########################################################################################
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# verilator makefile
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#########################################################################################
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#########################################################################################
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# general path variables
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#########################################################################################
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base_dir=$(abspath ../..)
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sim_dir=$(abspath .)
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PROJECT ?= example
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MODEL ?= TestHarness
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CONFIG ?= DefaultExampleConfig
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CFG_PROJECT ?= $(PROJECT)
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TB ?= TestDriver
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TOP ?= ExampleTop
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#########################################################################################
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# include shared variables
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#########################################################################################
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include $(base_dir)/Makefrag-Variables
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#########################################################################################
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# name of simulator (used to generate *.f arguments file)
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#########################################################################################
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sim_name = verilator
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sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
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sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
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#########################################################################################
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# vcs simulator types and rules
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#########################################################################################
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sim_prefix = simulator
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sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)
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sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug
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.PHONY: default debug
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default: $(sim)
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debug: $(sim_debug)
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CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
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LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
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#########################################################################################
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# import other necessary rules and variables
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#########################################################################################
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include $(base_dir)/Makefrag
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include $(sim_dir)/Makefrag-verilator
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ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
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-include $(build_dir)/$(long_name).d
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endif
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sim_blackboxes = \
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$(build_dir)/firrtl_black_box_resource_files.f
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rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
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sim_vsrcs = \
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$(VERILOG_FILE) \
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$(HARNESS_FILE) \
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$(SMEMS_FILE)
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include $(sim_dir)/Makefrag-Verilator
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#########################################################################################
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# verilator build paths and file names
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#########################################################################################
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model_dir = $(build_dir)/$(long_name)
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model_dir_debug = $(build_dir)/$(long_name).debug
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@ -45,6 +47,11 @@ model_header_debug = $(model_dir_debug)/V$(MODEL).h
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model_mk = $(model_dir)/V$(MODEL).mk
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model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
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#########################################################################################
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# build makefile fragment that builds the verilator sim rules
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#########################################################################################
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LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
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$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
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rm -rf $(build_dir)/$(long_name)
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mkdir -p $(build_dir)/$(long_name)
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@ -53,10 +60,6 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
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-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
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touch $@
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$(sim): $(model_mk)
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
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$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
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rm -rf $(build_dir)/$(long_name)
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mkdir -p $(build_dir)/$(long_name).debug
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@ -65,25 +68,26 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
|
|||
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
|
||||
touch $@
|
||||
|
||||
#########################################################################################
|
||||
# invoke make to make verilator sim rules
|
||||
#########################################################################################
|
||||
$(sim): $(model_mk)
|
||||
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
|
||||
|
||||
$(sim_debug): $(model_mk_debug)
|
||||
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
|
||||
|
||||
$(output_dir)/%.out: $(output_dir)/% $(sim)
|
||||
$(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
|
||||
|
||||
$(output_dir)/%.run: $(output_dir)/% $(sim)
|
||||
$(sim) +max-cycles=1000000 $< && touch $@
|
||||
|
||||
#########################################################################################
|
||||
# create a vcs vpd rule
|
||||
#########################################################################################
|
||||
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
|
||||
rm -f $@.vcd && mkfifo $@.vcd
|
||||
vcd2vpd $@.vcd $@ > /dev/null &
|
||||
$(sim_debug) -v$@.vcd +max-cycles=1000000 $<
|
||||
|
||||
run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
|
||||
|
||||
run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
|
||||
|
||||
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
|
||||
$(sim_debug) -v$@.vcd +max-cycles=$(timeout_cycles) $<
|
||||
|
||||
#########################################################################################
|
||||
# general cleanup rule
|
||||
#########################################################################################
|
||||
.PHONY: clean
|
||||
clean: clean-scala
|
||||
rm -rf generated-src ./simulator-*
|
||||
rm -rf $(build_dir) $(sim_prefix)-*
|
||||
|
|
|
|||
|
|
@ -1,7 +1,17 @@
|
|||
# Build and install our own Verilator, to work around versionining issues.
|
||||
VERILATOR_VERSION=3.920
|
||||
#########################################################################################
|
||||
# verilator installation makefrag
|
||||
#########################################################################################
|
||||
|
||||
#########################################################################################
|
||||
# verilator version, binary, and path
|
||||
#########################################################################################
|
||||
VERILATOR_VERSION=4.008
|
||||
VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
|
||||
INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
|
||||
|
||||
#########################################################################################
|
||||
# build and install our own verilator to work around versioning issues
|
||||
#########################################################################################
|
||||
$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
|
||||
$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
|
||||
touch $@
|
||||
|
|
@ -24,8 +34,11 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
|
|||
mkdir -p $(dir $@)
|
||||
wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
|
||||
|
||||
# Run Verilator to produce a fast binary to emulate this circuit.
|
||||
#########################################################################################
|
||||
# verilator binary and flags
|
||||
#########################################################################################
|
||||
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
|
||||
CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
|
||||
VERILATOR_FLAGS := --top-module $(MODEL) \
|
||||
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
|
||||
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
|
||||
|
|
@ -1,84 +1,102 @@
|
|||
#########################################################################################
|
||||
# vcs makefile
|
||||
#########################################################################################
|
||||
|
||||
#########################################################################################
|
||||
# general path variables
|
||||
#########################################################################################
|
||||
base_dir=$(abspath ../..)
|
||||
sim_dir=$(abspath .)
|
||||
|
||||
PROJECT ?= example
|
||||
MODEL ?= TestHarness
|
||||
CONFIG ?= DefaultExampleConfig
|
||||
CFG_PROJECT ?= $(PROJECT)
|
||||
TB ?= TestDriver
|
||||
TOP ?= ExampleTop
|
||||
#########################################################################################
|
||||
# include shared variables
|
||||
#########################################################################################
|
||||
include $(base_dir)/Makefrag-Variables
|
||||
|
||||
#########################################################################################
|
||||
# name of simulator (used to generate *.f arguments file)
|
||||
#########################################################################################
|
||||
sim_name = vcs
|
||||
|
||||
simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
|
||||
simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
|
||||
#########################################################################################
|
||||
# vcs simulator types and rules
|
||||
#########################################################################################
|
||||
sim_prefix = simv
|
||||
sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)
|
||||
sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug
|
||||
|
||||
default: $(simv)
|
||||
|
||||
debug: $(simv_debug)
|
||||
.PHONY: default debug
|
||||
default: $(sim)
|
||||
debug: $(sim_debug)
|
||||
|
||||
#########################################################################################
|
||||
# import other necessary rules and variables
|
||||
#########################################################################################
|
||||
include $(base_dir)/Makefrag
|
||||
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
|
||||
-include $(build_dir)/$(long_name).d
|
||||
endif
|
||||
|
||||
sim_blackboxes = \
|
||||
$(build_dir)/firrtl_black_box_resource_files.f
|
||||
|
||||
rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
|
||||
|
||||
sim_vsrcs = \
|
||||
$(VERILOG_FILE) \
|
||||
$(HARNESS_FILE) \
|
||||
$(SMEMS_FILE)
|
||||
|
||||
#########################################################################################
|
||||
# vcs binary and arguments
|
||||
#########################################################################################
|
||||
VCS = vcs -full64
|
||||
|
||||
VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
|
||||
+rad +v2k +vcs+lic+wait \
|
||||
+vc+list -CC "-I$(VCS_HOME)/include" \
|
||||
VCS_CC_OPTS = \
|
||||
-CC "-I$(VCS_HOME)/include" \
|
||||
-CC "-I$(RISCV)/include" \
|
||||
-CC "-std=c++11" \
|
||||
-CC "-Wl,-rpath,$(RISCV)/lib" \
|
||||
-f $(sim_blackboxes) -f $(sim_dotf) \
|
||||
$(RISCV)/lib/libfesvr.so \
|
||||
$(RISCV)/lib/libfesvr.so
|
||||
|
||||
VCS_NONCC_OPTS = \
|
||||
+lint=all,noVCDE,noONGS,noUI \
|
||||
-error=PCWM-L \
|
||||
-timescale=1ns/10ps \
|
||||
-quiet \
|
||||
+rad \
|
||||
+v2k \
|
||||
+vcs+lic+wait \
|
||||
+vc+list \
|
||||
-f $(sim_blackboxes) \
|
||||
-f $(sim_dotf) \
|
||||
-sverilog \
|
||||
+incdir+$(generated_dir) \
|
||||
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
|
||||
+incdir+$(build_dir) \
|
||||
+define+CLOCK_PERIOD=1.0 \
|
||||
$(sim_vsrcs) \
|
||||
+define+PRINTF_COND=$(TB).printf_cond \
|
||||
+define+STOP_COND=!$(TB).reset \
|
||||
+define+RANDOMIZE_MEM_INIT \
|
||||
+define+RANDOMIZE_REG_INIT \
|
||||
+define+RANDOMIZE_GARBAGE_ASSIGN \
|
||||
+define+RANDOMIZE_INVALID_ASSIGN \
|
||||
+libext+.v \
|
||||
+libext+.v
|
||||
|
||||
VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
|
||||
|
||||
#########################################################################################
|
||||
# helper rule to just make verilog files
|
||||
#########################################################################################
|
||||
.PHONY: verilog
|
||||
verilog: $(sim_vsrcs)
|
||||
|
||||
$(simv): $(sim_vsrcs) $(sim_dotf)
|
||||
#########################################################################################
|
||||
# vcs simulator rules
|
||||
#########################################################################################
|
||||
$(sim): $(sim_vsrcs) $(sim_dotf)
|
||||
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
|
||||
-debug_pp
|
||||
|
||||
$(simv_debug) : $(sim_vsrcs) $(sim_dotf)
|
||||
$(sim_debug) : $(sim_vsrcs) $(sim_dotf)
|
||||
rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
|
||||
+define+DEBUG -debug_pp
|
||||
|
||||
$(output_dir)/%.out: $(output_dir)/% $(simv)
|
||||
$(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
|
||||
|
||||
$(output_dir)/%.run: $(output_dir)/% $(simv)
|
||||
$(simv) +max-cycles=1000000 $< && touch $@
|
||||
|
||||
$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
|
||||
$(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $<
|
||||
|
||||
run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
|
||||
|
||||
run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
|
||||
|
||||
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
|
||||
|
||||
clean:
|
||||
rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h
|
||||
#########################################################################################
|
||||
# create a vcs vpd rule
|
||||
#########################################################################################
|
||||
$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
|
||||
$(sim_debug) +vcdplusfile=$@ +max-cycles=$(timeout_cycles) $<
|
||||
|
||||
#########################################################################################
|
||||
# general cleanup rule
|
||||
#########################################################################################
|
||||
.PHONY: clean
|
||||
clean: clean-scala
|
||||
rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
|
||||
|
|
|
|||
Loading…
Reference in New Issue