align rebar with tip of project-template master | fixes build issues
This commit is contained in:
abejgonzalez
parent
419d41239f
commit
7d887b212c
43
common.mk
43
common.mk
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@ -22,32 +22,12 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class
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#########################################################################################
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FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
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# this should match whatever the commonSettings version is in build.sbt
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BARSTOOLS_VER=1.0
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TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar
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MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar
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$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
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$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
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mkdir -p $(dir $@)
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cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
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touch $@
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$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala)
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cd $(base_dir) && $(SBT) "tapeout/assembly"
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$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala)
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cd $(base_dir) && $(SBT) "barstools-macros/assembly"
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.PHONY: jars
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jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
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#########################################################################################
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# tapeout and macrocompiler commands
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#########################################################################################
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TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR)
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MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR)
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#########################################################################################
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# create simulation args file rule
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#########################################################################################
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@ -68,15 +48,18 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
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#########################################################################################
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REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
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$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
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$(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir)
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$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
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cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
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cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
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$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR)
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$(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir)
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$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
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cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
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grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
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# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
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$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR)
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$(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops
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MACROCOMPILER_MODE ?= --mode synflops
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$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
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cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
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#########################################################################################
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# helper rule to just make verilog files
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@ -139,11 +122,3 @@ regression-tests = \
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run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
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run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
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run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
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#########################################################################################
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# general jar cleanup rule
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#########################################################################################
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.PHONY: clean-scala
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clean-scala:
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rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
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@ -1 +1,3 @@
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addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5")
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addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2")
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@ -56,7 +56,7 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
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rm -rf $(build_dir)/$(long_name)
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mkdir -p $(build_dir)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
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-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
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-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
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touch $@
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@ -64,7 +64,7 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
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rm -rf $(build_dir)/$(long_name)
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mkdir -p $(build_dir)/$(long_name).debug
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
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-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
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-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
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touch $@
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@ -55,7 +55,8 @@ VCS_NONCC_OPTS = \
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+v2k \
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+vcs+lic+wait \
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+vc+list \
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-f $(sim_blackboxes) \
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-f $(sim_top_blackboxes) \
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-f $(sim_harness_blackboxes) \
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-f $(sim_dotf) \
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-sverilog \
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+incdir+$(build_dir) \
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@ -82,6 +82,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
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out.close()
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}
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def resources(sim: Simulator): Seq[String] = Seq(
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"/testchipip/csrc/SimSerial.cc",
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"/csrc/SimDTM.cc",
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"/csrc/SimJTAG.cc",
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"/csrc/remote_bitbang.h",
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@ -1 +1 @@
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Subproject commit 0b9d74ada7e3271e82d665b09b3b9ff087c70f91
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Subproject commit e548210ef42e634e75cf283292685728114694c6
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10
variables.mk
10
variables.mk
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@ -33,10 +33,17 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
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FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
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ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
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VERILOG_FILE ?= $(build_dir)/$(long_name).top.v
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TOP_FIR ?= $(build_dir)/$(long_name).top.fir
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TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json
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HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
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HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir
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HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json
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SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v
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SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
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SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir
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sim_dotf ?= $(build_dir)/sim_files.f
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sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
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sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
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#########################################################################################
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# default sbt launch command
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@ -64,9 +71,6 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
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#########################################################################################
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# sources needed to run simulators
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#########################################################################################
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sim_blackboxes = \
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$(build_dir)/firrtl_black_box_resource_files.f
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sim_vsrcs = \
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$(VERILOG_FILE) \
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$(HARNESS_FILE) \
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