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hanchenye-llvm-project/llvm/test/CodeGen/Hexagon
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Matthias Braun 868bbd4022 ScheduleDAGInstrs: Fix fixupKills() 
Rewrite fixupKills() to use the LivePhysRegs class. Simplifies the code
and fixes a bug where the CSR registers in return blocks where missed
leading to invalid kill flags. Also remove the unnecessary rule that we
wouldn't set kill flags on tied operands.

No tests as I have an upcoming commit improving MachineVerifier checks
to catch these cases in multiple existing lit tests.

llvm-svn: 304055
 		2017-05-27 02:50:50 +00:00
..
intrinsics [Hexagon] Add intrinsics for masked vector stores 2017-02-22 21:23:09 +00:00
loop-idiom [Hexagon] Avoid infinite loops in HexagonLoopIdiomRecognition 2017-03-23 23:01:22 +00:00
vect [Hexagon] Generate extract instructions more aggressively 2017-02-28 23:27:33 +00:00
Atomics.ll [Hexagon] Handle expansion of cmpxchg 2016-06-22 16:07:10 +00:00
BranchPredict.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
NVJumpCmp.ll
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SUnit-boundary-prob.ll [Hexagon] segv while processing SUnit with nullNodePtr 2016-09-17 16:21:09 +00:00
absaddr-store.ll [Hexagon] Fix printing the address operand of S2_storerinewabs 2016-04-19 20:20:33 +00:00
absimm.ll
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adde.ll [Hexagon] Propagate zext of i1 into arithmetic code in selection DAG 2017-03-09 16:29:30 +00:00
addh-sext-trunc.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
addh-shifted.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
addh.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
addr-calc-opt.ll [Hexagon] Improve balancing of address calculation 2016-07-29 15:15:35 +00:00
addrmode-globoff.mir [Hexagon] Generate proper offset in opt-addr-mode 2017-04-19 15:15:51 +00:00
addrmode-indoff.ll
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adjust-latency-stackST.ll [Hexagon] Adjust latency between allocframe and the first store on stack 2017-05-03 15:33:09 +00:00
alu64.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
always-ext.ll
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anti-dep-partial.mir Move .mir tests to appropriate directories 2016-12-09 19:08:15 +00:00
args.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
ashift-left-right.ll
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avoid-predspill-calleesaved.ll [Hexagon] Start using regmasks on calls 2017-02-17 22:14:51 +00:00
avoid-predspill.ll
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barrier-flag.ll
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base-offset-addr.ll
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base-offset-post.ll
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bit-bitsplit-at.ll [Hexagon] Fixes to the bitsplit generation 2017-03-09 22:02:14 +00:00
bit-bitsplit-src.ll [Hexagon] Generate bitsplit instruction 2017-03-07 23:08:35 +00:00
bit-bitsplit.ll [Hexagon] Generate bitsplit instruction 2017-03-07 23:08:35 +00:00
bit-eval.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
bit-ext-sat.ll [Hexagon] Handle saturations in Hexagon bit tracker 2017-02-23 22:11:52 +00:00
bit-extract-off.ll [Hexagon] Use correct offset when extracting from the high word 2017-03-08 15:46:28 +00:00
bit-extract.ll [Hexagon] Generate extract instructions more aggressively 2017-02-28 23:27:33 +00:00
bit-extractu-half.ll
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bit-gen-rseq.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
bit-has.ll [Hexagon] Check for presence before looking registers up in bit tracker 2017-03-07 23:12:04 +00:00
bit-loop-rc-mismatch.ll [Hexagon] Gracefully handle reg class mismatch in HexagonLoopReschedule 2016-07-26 19:17:13 +00:00
bit-loop.ll
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bit-phi.ll [Hexagon] Do not insert instructions before PHI nodes 2017-03-07 14:20:19 +00:00
bit-rie.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
bit-skip-byval.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
bit-validate-reg.ll [Hexagon] Generate extract instructions more aggressively 2017-02-28 23:27:33 +00:00
bit-visit-flowq.ll [Hexagon] Clear the flow queue after visiting a single instruction 2016-09-13 14:36:55 +00:00
bitconvert-vector.ll [Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1) 2016-06-27 15:08:22 +00:00
bitmanip.ll [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE 2017-02-23 15:02:09 +00:00
block-addr.ll [Hexagon] Early-if-convert branches that may exit the loop 2017-03-06 17:24:04 +00:00
block-ranges-nodef.ll [Hexagon] Properly close live range in HexagonBlockRanges ---add testcase 2016-04-22 17:30:13 +00:00
branch-folder-hoist-kills.mir Remove stale live-ins in the branch folder 2017-05-05 12:20:07 +00:00
branch-non-mbb.ll
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branchfolder-keep-impdef.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
brev_ld.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
brev_st.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
bugAsmHWloop.ll
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build-vector-shuffle.ll [Hexagon] Better handling of HVX vector lowering 2016-09-13 21:16:07 +00:00
builtin-expect.ll [Hexagon] Pick the right branch opcode depending on branch probabilities 2017-03-02 21:49:49 +00:00
builtin-prefetch-offset.ll
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builtin-prefetch.ll
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calling-conv-2.ll
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callr-dep-edge.ll [ScheduleDAG] Make sure to process all def operands before any use operands 2016-05-10 16:50:30 +00:00
cext-check.ll [Hexagon] Simplify HexagonInstrInfo::isPredicable 2016-05-16 16:56:10 +00:00
cext-valid-packet1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
cext-valid-packet2.ll
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cext.ll
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cexti16.ll
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cfgopt-fall-through.ll [Hexagon] Do not move a block if it is on a fall-through path 2017-04-28 21:54:11 +00:00
cfi-late.ll [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
cfi-offset.ll [Hexagon] Use offsets relative to FP+8 in .cfi_offset instructions 2016-05-11 14:53:07 +00:00
checktabs.ll
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circ-load-isel.ll [Hexagon] Remove dead nodes from SelectionDAG to avoid cycles 2016-05-13 18:48:15 +00:00
circ_ld.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
circ_ldd_bug.ll
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circ_ldw.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
circ_st.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
clr_set_toggle.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
cmp-extend.ll
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cmp-promote.ll
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cmp-to-genreg.ll
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cmp-to-predreg.ll
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cmp.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
cmp_pred.ll
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cmp_pred2.ll
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cmp_pred_reg.ll
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cmpb-eq.ll
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cmpb_pred.ll
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combine.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
combine_ir.ll
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common-gep-basic.ll
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common-gep-icm.ll
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compound.ll [Hexagon] Start using regmasks on calls 2017-02-17 22:14:51 +00:00
const-pool-tf.ll [Hexagon] Improve test to check for @PCREL, only run llc, not opt -> llc. 2016-08-16 13:10:09 +00:00
const64.ll
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constp-clb.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-combine-neg.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
constp-ctb.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-extract.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-physreg.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-rewrite-branches.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-rseq.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
constp-vsplat.ll [Hexagon] Implement MI-level constant propagation 2016-07-28 20:01:59 +00:00
convert-to-dot-old.ll [Hexagon] Pick a dot-old instruction that matches the architecture 2017-03-06 17:03:16 +00:00
convertdptoint.ll
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convertdptoll.ll
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convertsptoint.ll
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convertsptoll.ll
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copy-to-combine-dbg.ll [Hexagon] Check for block end when skipping debug instructions 2016-08-24 22:36:35 +00:00
csr-func-usedef.ll [Hexagon] Register save/restore functions do not follow regular conventions 2016-04-25 17:49:44 +00:00
ctor.ll
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dadd.ll
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dead-store-stack.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
dmul.ll
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double.ll
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doubleconvert-ieee-rnd-near.ll
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dsub.ll
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dualstore.ll
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duplex.ll
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early-if-conversion-bug1.ll
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early-if-merge-loop.ll [Hexagon] Early-if-convert branches that may exit the loop 2017-03-06 17:24:04 +00:00
early-if-phi-i1.ll [Hexagon] Add -march=hexagon to a testcase 2017-03-21 16:59:40 +00:00
early-if-spare.ll
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early-if-vecpi.ll [Hexagon] Post-increment loads/stores enhancements 2016-07-26 20:30:30 +00:00
early-if-vecpred.ll [Hexagon] Skip blocks that define vector predicate registers in early-if 2017-03-02 18:10:59 +00:00
early-if.ll
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eh_return.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
eliminate-pred-spill.ll [Hexagon] Use -mattr to select HVX mode in a testcase, NFC 2017-04-05 19:46:37 +00:00
expand-condsets-basic.ll
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expand-condsets-dead-bad.ll [Hexagon] Mark dead defs as <dead> in expand-condsets 2017-03-06 17:09:06 +00:00
expand-condsets-dead-pred.ll [Hexagon] Mark dead defs as <dead> in expand-condsets 2017-03-06 17:09:06 +00:00
expand-condsets-def-undef.mir [Hexagon] Separate Hexagon subreg indices for different register classes 2016-11-09 16:19:08 +00:00
expand-condsets-extend.ll [Hexagon] Deal with undefs when extending live intervals 2016-09-01 13:59:35 +00:00
expand-condsets-impuse.mir [Hexagon] Maintain kill flags through splitting in expand-condsets 2016-10-28 15:50:22 +00:00
expand-condsets-pred-undef.ll [Hexagon] Teach mux expansion how to deal with undef predicates 2016-04-22 16:47:01 +00:00
expand-condsets-rm-reg.mir Bring back 2>&1 redirection for this test 2017-02-22 19:16:33 +00:00
expand-condsets-rm-segment.ll
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expand-condsets-same-inputs.mir [Hexagon] Don't expand mux instructions with both sources identical 2016-10-31 15:45:09 +00:00
expand-condsets-undef.ll
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expand-condsets-undef2.ll [Hexagon] Check for empty live interval 2016-08-19 14:29:43 +00:00
expand-vstorerw-undef.ll [Hexagon] Handle spills of partially defined double vector registers 2016-10-21 16:38:29 +00:00
expand-vstorerw-undef2.ll [Hexagon] Remove dead defs from the live set when expanding wstores 2017-01-18 23:11:40 +00:00
extload-combine.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
extract-basic.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fadd.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fcmp.ll
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find-loop-instr.ll [Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructions 2017-02-02 19:36:37 +00:00
fixed-spill-mutable.ll Fixed spill stack objects are mutable 2016-08-31 13:52:17 +00:00
float-amode.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
float.ll
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floatconvert-ieee-rnd-near.ll
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fminmax.ll [Hexagon] Improvements to handling and generation of FP instructions 2016-08-19 13:34:31 +00:00
fmul.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
frame-offset-overflow.ll [Hexagon] Check for offset overflow when reserving scavenging slots 2016-08-01 17:15:30 +00:00
frame.ll
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fsel.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fsub.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
fusedandshift.ll [Hexagon] Generate extract instructions more aggressively 2017-02-28 23:27:33 +00:00
gp-plus-offset-load.ll
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gp-plus-offset-store.ll
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gp-rel.ll [Hexagon] Adding gp+ to the syntax of gp-relative instructions 2017-02-06 23:18:57 +00:00
hwloop-cleanup.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop-const.ll
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hwloop-crit-edge.ll [LSR] Don't try and create post-inc expressions on non-rotated loops 2016-08-15 07:53:03 +00:00
hwloop-dbg.ll [PR27284] Reverse the ownership between DICompileUnit and DISubprogram. 2016-04-15 15:57:41 +00:00
hwloop-le.ll
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hwloop-loop1.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
hwloop-lt.ll
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hwloop-lt1.ll
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hwloop-missed.ll
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hwloop-ne.ll
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hwloop-noreturn-call.ll [Hexagon] Allow non-returning calls in hardware loops 2016-08-11 21:14:25 +00:00
hwloop-ph-deadcode.ll
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hwloop-pos-ivbump1.ll
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hwloop-preh.ll [Hexagon] Find speculative loop preheader in hardware loop generation 2016-07-27 21:20:54 +00:00
hwloop-preheader.ll
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hwloop-range.ll
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hwloop-recursion.ll
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hwloop-wrap.ll
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hwloop-wrap2.ll
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hwloop1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop3.ll
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hwloop4.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
hwloop5.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
i1_VarArg.ll
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i8_VarArg.ll
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i16_VarArg.ll
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idxload-with-zero-offset.ll
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ifcvt-diamond-bad.ll
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ifcvt-diamond-bug-2016-08-26.ll [Hexagon] Fix typo in HexagonEarlyIfCConv.cpp 2017-03-31 20:36:00 +00:00
ifcvt-edge-weight.ll
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ifcvt-impuse-livein.mir MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
ifcvt-live-subreg.mir IfConversion: Add implicit uses for redefined regs with live subregisters 2016-09-28 20:07:41 +00:00
ifcvt-simple-bprob.ll [IfConversion] Only renormalize probabilities if branches are analyzable 2017-03-06 19:12:42 +00:00
indirect-br.ll
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inline-asm-hexagon.ll [Hexagon] Add support for proper handling of H and L constraints 2016-07-26 17:31:02 +00:00
inline-asm-i1.ll [Hexagon] Add RUN line to test 2016-08-19 19:36:35 +00:00
inline-asm-qv.ll [Hexagon] Recognize "q" and "v" in inline-asm as register constraints 2016-05-18 14:34:51 +00:00
inline-asm-vecpred128.ll [Hexagon] Properly handle 'q' constraint in 128-byte vector mode 2017-03-02 17:50:24 +00:00
insert-basic.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
insert4.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
is-legal-void.ll [Hexagon] Do not check alignment for unsized types in isLegalAddressingMode 2016-08-03 15:06:18 +00:00
isel-exti1.ll [Hexagon] Fix instruction selection for sign-extending i1 to i64 2017-02-28 22:37:01 +00:00
isel-i1arg-crash.ll [Hexagon] Fix lowering of formal arguments of type i1 2017-03-01 17:30:10 +00:00
isel-op-zext-i1.ll [Hexagon] Propagate zext of i1 into arithmetic code in selection DAG 2017-03-09 16:29:30 +00:00
lit.local.cfg
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livephysregs-lane-masks.mir Handle lane masks in LivePhysRegs when adding live-ins 2016-10-12 22:53:41 +00:00
livephysregs-lane-masks2.mir Handle non-~0 lane masks on live-in registers in LivePhysRegs 2016-10-28 20:06:37 +00:00
loadi1-G0.ll
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loadi1-v4-G0.ll
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loadi1-v4.ll
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loadi1.ll
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long-calls.ll [Hexagon] Add target feature to generate long calls 2016-07-25 14:42:11 +00:00
loop-prefetch.ll [Hexagon] Use loop data prefetch on Hexagon 2016-07-22 14:22:43 +00:00
lower-extract-subvector.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
macint.ll
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maxd.ll
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maxh.ll
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maxud.ll
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maxuw.ll
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maxw.ll
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mem-fi-add.ll
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memcpy-likely-aligned.ll
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memops-stack.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
memops.ll [Hexagon] Improve patterns with stack-based addressing 2016-07-15 15:35:52 +00:00
memops1.ll
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memops2.ll
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memops3.ll
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mind.ll
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minu-zext-8.ll
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minu-zext-16.ll
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minud.ll
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minuw.ll
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minw.ll
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misaligned-access.ll
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misaligned_double_vector_store_not_fast.ll [Hexagon] Fix test that uses -debug-only to require asserts. 2016-07-29 21:44:33 +00:00
misched-top-rptracker-sync.ll Reset the TopRPTracker's position in ScheduleDAGMILive::initQueues 2016-04-28 19:17:44 +00:00
mpy.ll
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mulhs.ll [Hexagon] Add pattern for 64-bit mulhs 2016-08-08 19:24:25 +00:00
multi-cycle.ll [Hexagon] Don't ignore mult-cycle latency information 2017-05-02 18:12:19 +00:00
mux-basic.ll
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newvalueSameReg.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
newvaluejump.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
newvaluejump2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
newvaluejump3.ll [Hexagon] Avoid IMPLICIT_DEFs as new-value producers 2017-02-23 17:47:34 +00:00
newvaluestore.ll [Hexagon] Enable the post-RA scheduler 2016-05-26 19:44:28 +00:00
opt-addr-mode.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
opt-fabs.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
opt-fneg.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
opt-spill-volatile.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
packetize-cfi-location.ll [Hexagon] Insert CFI instructions before throwing calls 2016-07-28 19:13:46 +00:00
packetize-return-arg.ll [Hexagon] Packetize return value setup with the return instruction 2016-08-23 16:01:01 +00:00
packetize-tailcall-arg.ll [Hexagon] Packetize function call arguments with tail call instructions 2016-07-14 19:30:55 +00:00
packetize_cond_inst.ll
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peephole-kill-flags.ll [Hexagon] Clear kill flags from modified registers in peephole optimizer 2016-08-04 14:17:16 +00:00
peephole-op-swap.ll [Hexagon] Fix operand swapping in HexagonPeephole 2016-04-19 21:36:24 +00:00
pic-jumptables.ll
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pic-local.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
pic-regusage.ll
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pic-simple.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
pic-static.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
plt-rel.ll [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL 2017-05-02 18:15:33 +00:00
post-inc-aa-metadata.ll Propagate TBAA info in SelectionDAG::getIndexedLoad 2016-08-29 19:50:15 +00:00
post-ra-kill-update.mir ScheduleDAGInstrs: Fix fixupKills() 2017-05-27 02:50:50 +00:00
postinc-load.ll
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postinc-offset.ll
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postinc-store.ll
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pred-absolute-store.ll [RDF] Remove the map of reaching defs from copy propagation 2017-03-10 22:44:24 +00:00
pred-gp.ll
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pred-instrs.ll
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predicate-copy.ll
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predicate-logical.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
predicate-rcmp.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
propagate-vcombine.ll [Hexagon] Recognize vcombine in copy propagation 2016-08-02 21:49:20 +00:00
rdf-copy-undef2.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
rdf-copy.ll Codegen: Tail Merge: Be less aggressive with special cases. 2016-08-10 18:36:18 +00:00
rdf-cover-use.ll [RDF] Remove covered parts of reached uses for phi and use in same block 2017-05-05 22:10:32 +00:00
rdf-dead-loop.ll
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rdf-def-mask.ll [RDF] Correctly calculate lane masks for defs 2017-04-28 21:57:53 +00:00
rdf-extra-livein.ll [RDF] Fix liveness propagation through shadows 2016-10-03 20:17:20 +00:00
rdf-filter-defs.ll [RDF] Fix live def propagation through basic block 2016-10-05 20:08:09 +00:00
rdf-ignore-undef.ll [RDF] Ignore undef use operands 2016-09-06 17:03:13 +00:00
rdf-inline-asm-fixed.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
rdf-inline-asm.ll [RDF] Improve handling of inline-asm 2016-04-28 20:33:33 +00:00
rdf-multiple-phis-up.ll [RDF] Further improve handling of multiple phis reached from shadows 2016-09-08 20:48:42 +00:00
rdf-phi-shadows.ll [RDF] Fix liveness analysis for phi nodes with shadow uses 2016-09-07 20:37:05 +00:00
rdf-phi-up.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
rdf-reset-kills.ll [RDF] Consider register as live if any alias is live 2016-04-20 14:33:23 +00:00
readcyclecounter.ll [Hexagon] Implement @llvm.readcyclecounter() 2017-02-22 22:28:47 +00:00
reg-scavengebug-3.ll
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reg-scavenger-valid-slot.ll When looking for a spill slot in reg scavenger, find one that matches RC 2016-05-18 18:16:00 +00:00
regalloc-bad-undef.mir Add extra operand to CALLSEQ_START to keep frame part set up previously 2017-05-09 13:35:13 +00:00
regalloc-block-overlap.ll Treat segment [B, E) as not overlapping block with boundaries [A, B) 2017-01-18 23:12:19 +00:00
relax.ll Revert r265817 2016-04-08 18:15:37 +00:00
remove-endloop.ll
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remove_lsr.ll
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restore-single-reg.ll [Hexagon] Only use restore functions for single register at -Oz 2016-03-28 14:52:21 +00:00
ret-struct-by-val.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
runtime-stkchk.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
sdata-array.ll [Hexagon] Expand handling of the small-data/bss section 2016-04-21 18:56:45 +00:00
sdata-basic.ll [Hexagon] Expand handling of the small-data/bss section 2016-04-21 18:56:45 +00:00
sdr-basic.ll
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sdr-shr32.ll
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section_7275.ll [Hexagon] Adding gp+ to the syntax of gp-relative instructions 2017-02-06 23:18:57 +00:00
select-instr-align.ll [Hexagon] Improve handling of unaligned vector loads and stores 2016-03-28 15:43:03 +00:00
sf-min-max.ll [Hexagon] Add extra patterns for single-precision min/max instructions 2016-08-10 17:56:24 +00:00
sffms.ll [Hexagon] Improvements to handling and generation of FP instructions 2016-08-19 13:34:31 +00:00
shrink-frame-basic.ll
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signed_immediates.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
simple_addend.ll
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simpletailcall.ll
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split-const32-const64.ll [Hexagon] Simplify the SplitConst32/64 pass 2016-08-10 18:05:47 +00:00
stack-align1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
stack-align2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
stack-alloca1.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
stack-alloca2.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
static.ll [Hexagon] Adding gp+ to the syntax of gp-relative instructions 2017-02-06 23:18:57 +00:00
store-shift.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
store-widen-aliased-load.ll
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store-widen-negv.ll
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store-widen-negv2.ll
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store-widen.ll
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storerd-io-over-rr.ll [Hexagon] Prefer _io over _rr for 64-bit store with constant offset 2016-08-02 18:50:05 +00:00
storerinewabs.ll [Hexagon] Fix printing the address operand of S2_storerinewabs 2016-04-19 20:20:33 +00:00
struct_args.ll [Hexagon] Bitwise operations for insert/extract word not simplified 2016-07-26 18:30:11 +00:00
struct_args_large.ll
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sube.ll [Hexagon] Propagate zext of i1 into arithmetic code in selection DAG 2017-03-09 16:29:30 +00:00
subi-asl.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-const-tc.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-dag-phi.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
swp-epilog-phi10.ll Fix two bugs in the pipeliner in renaming phis in the prolog and epilog 2016-12-22 18:49:55 +00:00
swp-epilog-reuse-1.ll [Pipeliner] Fix an asssert due to invalid Phi in the epilog 2016-08-16 14:29:24 +00:00
swp-epilog-reuse.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
swp-matmul-bitext.ll [Hexagon] Use automatically-generated scheduling information for HVX 2017-05-03 20:10:36 +00:00
swp-max.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-multi-loops.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-prolog-phi4.ll Fix two bugs in the pipeliner in renaming phis in the prolog and epilog 2016-12-22 18:49:55 +00:00
swp-stages4.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-stages5.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-vect-dotprod.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
swp-vmult.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
swp-vsum.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tail-call-mem-intrinsics.ll
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tail-call-trunc.ll
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tail-dup-subreg-abort.ll
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tail-dup-subreg-map.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tailcall_fastcc_ccc.ll [Hexagon] Allow tail-call optimization when mixing C and fast calling conv 2016-08-19 15:02:18 +00:00
tfr-to-combine.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tls_pic.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
tls_static.ll Set some tests to an unknown vendor and OS 2016-10-03 21:58:20 +00:00
two-crash.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
undo-dag-shift.ll [Hexagon] Undo shift folding where it could simplify addressing mode 2017-02-24 23:34:24 +00:00
union-1.ll
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unreachable-mbb-phi-subreg.mir Properly handle PHIs with subregisters in UnreachableBlockElim 2017-04-28 21:56:33 +00:00
usr-ovf-dep.ll
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v6vec-vprint.ll [Hexagon] vector store print tracing. 2016-08-25 13:35:48 +00:00
v60-cur.ll MachinePipeliner pass that implements Swing Modulo Scheduling 2016-07-29 16:44:44 +00:00
v60-vsel1.ll [Hexagon] Do not expand ISD::SELECT for HVX vectors 2016-10-27 14:30:16 +00:00
v60Intrins.ll [Hexagon] Enable the post-RA scheduler 2016-05-26 19:44:28 +00:00
v60Vasr.ll
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v60small.ll
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vaddh.ll [Hexagon] Replace instruction definitions with auto-generated ones 2017-02-10 15:33:13 +00:00
validate-offset.ll
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vassign-to-combine.ll [Hexagon] Create vcombine in HexagonCopyToCombine 2016-08-18 14:12:34 +00:00
vdmpy-halide-test.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
vec-pred-spill1.ll
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vector-align.ll
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vector-ext-load.ll [Hexagon] Expand sext- and zextloads of vector types, not just extloads 2016-09-08 17:42:14 +00:00
vload-postinc-sel.ll [Hexagon] Simplify (+fix) instruction selection for indexed loads/stores 2016-06-24 21:27:17 +00:00
vmpa-halide-test.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
vpack_eo.ll [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVX 2016-07-29 16:44:27 +00:00
vselect-pseudo.ll [Hexagon] Expand VSelect pseudo instructions 2016-05-12 19:16:02 +00:00
vsplat-isel.ll [Hexagon] Properly handle instruction selection of vsplat intrinsics 2016-05-12 17:21:40 +00:00
zextloadi1.ll [Hexagon] Optimize addressing modes for load/store 2016-04-29 15:49:13 +00:00