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[Hexagon] Do not expand ISD::SELECT for HVX vectors 

llvm-svn: 285297
This commit is contained in:
Krzysztof Parzyszek 2016-10-27 14:30:16 +00:00
parent 01e755eab1
commit 046da74699
3 changed files with 88 additions and 16 deletions
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11
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -1957,7 +1957,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
// Misc:
ISD::SELECT, ISD::ConstantPool,
ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
// Vector:
ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
@ -1979,12 +1979,15 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setTruncStoreAction(VT, TargetVT, Expand);
}
// Normalize all inputs to SELECT to be vectors of i32.
if (VT.getVectorElementType() != MVT::i32) {
MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
setOperationAction(ISD::SELECT, VT, Promote);
AddPromotedToType(ISD::SELECT, VT, VT32);
}
setOperationAction(ISD::SRA, VT, Custom);
setOperationAction(ISD::SHL, VT, Custom);
setOperationAction(ISD::SRL, VT, Custom);
setOperationAction(ISD::BR_CC, VT, Expand);
setOperationAction(ISD::SELECT_CC, VT, Expand);
}
// Types natively supported:

24
llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td
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@ -977,18 +977,18 @@ let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
"", []>, Requires<[HasV60T,UseHVXDbl]>;
}
class VSelPat<ValueType VT, RegisterClass RC, InstHexagon MI>
: Pat<(selectcc I32:$lhs, I32:$rhs, (VT RC:$tval), (VT RC:$fval), SETEQ),
(MI (C2_cmpeq I32:$lhs, I32:$rhs), RC:$tval, RC:$fval)>;
def: VSelPat<v16i32, VectorRegs, PS_vselect>,
Requires<[HasV60T,UseHVXSgl]>;
def: VSelPat<v32i32, VecDblRegs, PS_wselect>,
Requires<[HasV60T,UseHVXSgl]>;
def: VSelPat<v32i32, VectorRegs128B, PS_vselect_128B>,
Requires<[HasV60T,UseHVXDbl]>;
def: VSelPat<v64i32, VecDblRegs128B, PS_wselect_128B>,
Requires<[HasV60T,UseHVXDbl]>;
let Predicates = [HasV60T,UseHVXSgl] in {
def: Pat<(select I1:$Pu, (v16i32 VectorRegs:$Vs), VectorRegs:$Vt),
(PS_vselect I1:$Pu, VectorRegs:$Vs, VectorRegs:$Vt)>;
def: Pat<(select I1:$Pu, (v32i32 VecDblRegs:$Vs), VecDblRegs:$Vt),
(PS_wselect I1:$Pu, VecDblRegs:$Vs, VecDblRegs:$Vt)>;
}
let Predicates = [HasV60T,UseHVXDbl] in {
def: Pat<(select I1:$Pu, (v32i32 VectorRegs128B:$Vs), VectorRegs128B:$Vt),
(PS_vselect_128B I1:$Pu, VectorRegs128B:$Vs, VectorRegs128B:$Vt)>;
def: Pat<(select I1:$Pu, (v64i32 VecDblRegs128B:$Vs), VecDblRegs128B:$Vt),
(PS_wselect_128B I1:$Pu, VecDblRegs128B:$Vs, VecDblRegs128B:$Vt)>;
}
let hasNewValue = 1 in

69
llvm/test/CodeGen/Hexagon/v60-vsel1.ll Normal file
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@ -0,0 +1,69 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: if (p{{[0-3]}}) v{{[0-9]+}} = v{{[0-9]+}}
target triple = "hexagon"
; Function Attrs: nounwind
define void @fast9_detect_coarse(i8* nocapture readnone %img, i32 %xsize, i32 %stride, i32 %barrier, i32* nocapture %bitmask, i32 %boundary) #0 {
entry:
%0 = bitcast i32* %bitmask to <16 x i32>*
%1 = mul i32 %boundary, -2
%sub = add i32 %1, %xsize
%rem = and i32 %boundary, 63
%add = add i32 %sub, %rem
%2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1)
%3 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
%4 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %add)
%5 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %3, <512 x i1> %4, i32 12)
%and4 = and i32 %add, 511
%cmp = icmp eq i32 %and4, 0
%sMaskR.0 = select i1 %cmp, <16 x i32> %2, <16 x i32> %5
%cmp547 = icmp sgt i32 %add, 0
br i1 %cmp547, label %for.body.lr.ph, label %for.end
for.body.lr.ph: ; preds = %entry
%6 = tail call <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %boundary)
%7 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1> %6, i32 16843009)
%8 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %7)
%9 = add i32 %rem, %xsize
%10 = add i32 %9, -1
%11 = add i32 %10, %1
%12 = lshr i32 %11, 9
%13 = mul i32 %12, 16
%14 = add nuw nsw i32 %13, 16
%scevgep = getelementptr i32, i32* %bitmask, i32 %14
br label %for.body
for.body: ; preds = %for.body.lr.ph, %for.body
%i.050 = phi i32 [ %add, %for.body.lr.ph ], [ %sub6, %for.body ]
%sMask.049 = phi <16 x i32> [ %8, %for.body.lr.ph ], [ %2, %for.body ]
%optr.048 = phi <16 x i32>* [ %0, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]
%15 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> undef, <16 x i32> %sMask.049)
%incdec.ptr = getelementptr inbounds <16 x i32>, <16 x i32>* %optr.048, i32 1
store <16 x i32> %15, <16 x i32>* %optr.048, align 64
%sub6 = add nsw i32 %i.050, -512
%cmp5 = icmp sgt i32 %sub6, 0
br i1 %cmp5, label %for.body, label %for.cond.for.end_crit_edge
for.cond.for.end_crit_edge: ; preds = %for.body
%scevgep51 = bitcast i32* %scevgep to <16 x i32>*
br label %for.end
for.end: ; preds = %for.cond.for.end_crit_edge, %entry
%optr.0.lcssa = phi <16 x i32>* [ %scevgep51, %for.cond.for.end_crit_edge ], [ %0, %entry ]
%16 = load <16 x i32>, <16 x i32>* %optr.0.lcssa, align 64
%17 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %16, <16 x i32> %sMaskR.0)
store <16 x i32> %17, <16 x i32>* %optr.0.lcssa, align 64
ret void
}
declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
declare <512 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1
declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <512 x i1>, i32) #1
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1
declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1
declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
attributes #1 = { nounwind readnone }