456db39ea9
ARM callseq_end should have a input flag operand so it would be scheduled right after the call.
...
llvm-svn: 33832
2007-02-03 09:11:58 +00:00
83f35170fa
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
...
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
77c15ded10
Code clean up. Use def : pat instead of defining new instructions.
...
llvm-svn: 33368
2007-01-19 20:27:35 +00:00
10043e215b
ARM backend contribution from Apple.
...
llvm-svn: 33353
2007-01-19 07:51:42 +00:00
fd68718467
implement missing compares
...
patch by Lauro
bug fixed by me
llvm-svn: 32795
2006-12-31 18:52:39 +00:00
7251e57ff8
Implement SELECT_CC (f32/f64) for ARM.
...
llvm-svn: 32762
2006-12-28 13:11:14 +00:00
865b979833
remove duplicated line
...
bug noticed by Lauro
llvm-svn: 32761
2006-12-28 12:51:40 +00:00
d0ced3f1e8
This patch defines extloadi1 and fixes an internal compiler error on
...
arm.
llvm-svn: 32760
2006-12-26 19:30:42 +00:00
67d1c8ae0e
more general matching of the MVN instruction
...
llvm-svn: 32484
2006-12-12 17:10:13 +00:00
9fa0a26808
use MVN to handle small negative constants
...
llvm-svn: 32459
2006-12-12 01:03:11 +00:00
1bbe581d0f
add mvn
...
llvm-svn: 32454
2006-12-12 00:37:38 +00:00
87f4382163
fix truncstorei1
...
llvm-svn: 32364
2006-12-08 18:41:21 +00:00
5f7ab1b964
implement load effective address similar to the alpha backend
...
remove lea_addri and the now unused memri addressing mode
llvm-svn: 31592
2006-11-09 13:58:55 +00:00
708cb60588
initial implementation of addressing mode 2
...
TODO: fix lea_addri
llvm-svn: 31552
2006-11-08 17:07:32 +00:00
9ac6442db6
remove dead/redundant vars
...
llvm-svn: 31435
2006-11-03 23:48:56 +00:00
0cd8d14c7c
implement zextload bool and truncstore bool
...
llvm-svn: 31348
2006-11-01 14:13:27 +00:00
aaeede0aa2
implement uncond branch insertion, mark branches with isBranch.
...
llvm-svn: 31160
2006-10-24 16:47:57 +00:00
b43efe86f5
implement STRB and STRH
...
llvm-svn: 31138
2006-10-23 20:34:27 +00:00
336d62e99a
use Pat to implement extloadi8 and extloadi16
...
llvm-svn: 31052
2006-10-19 17:05:03 +00:00
f8274c0318
implement undef
...
llvm-svn: 31049
2006-10-19 13:45:00 +00:00
ff62819e2f
implement extloadi8 and extloadi16
...
llvm-svn: 31047
2006-10-19 12:45:04 +00:00
bad440742e
add blx
...
llvm-svn: 31037
2006-10-18 16:21:43 +00:00
01dd97a8aa
add isTerminatortto b and bcond
...
llvm-svn: 31036
2006-10-18 16:20:57 +00:00
3968263ca8
add the FPUnaryOp and DFPUnaryOp classes
...
llvm-svn: 31013
2006-10-17 20:45:22 +00:00
99bf133d58
add FABSS and FABSD
...
llvm-svn: 31012
2006-10-17 20:33:13 +00:00
2d7d14262a
remove extra [] in stores
...
llvm-svn: 31008
2006-10-17 18:29:14 +00:00
19398ec86e
initial implementation of addressing mode 5
...
llvm-svn: 31002
2006-10-17 18:04:53 +00:00
418c8e69bb
add FSTD and FSTS
...
llvm-svn: 30996
2006-10-17 13:36:07 +00:00
c31ee94920
add FCPYS and FCPYD
...
llvm-svn: 30995
2006-10-17 13:13:23 +00:00
afdd47ace4
add fdivs e fdivd
...
llvm-svn: 30988
2006-10-16 21:50:04 +00:00
f719c5f43d
expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS
...
llvm-svn: 30987
2006-10-16 21:10:32 +00:00
e341d60f53
define the DFPBinOp class
...
llvm-svn: 30981
2006-10-16 18:39:22 +00:00
f63752f94b
add the FPBinOp class
...
llvm-svn: 30980
2006-10-16 18:32:36 +00:00
b23dc14135
define the Addr1BinOp class
...
llvm-svn: 30979
2006-10-16 18:18:14 +00:00
203922d083
define the IntBinOp class and use it to implement the multiply instructions
...
llvm-svn: 30978
2006-10-16 17:57:20 +00:00
c4abf8dc5b
fix assembly syntax
...
llvm-svn: 30977
2006-10-16 17:38:12 +00:00
677ee8390d
implement LDRB, LDRSB, LDRH and LDRSH
...
llvm-svn: 30976
2006-10-16 17:17:22 +00:00
595dc4c884
implement smull and umull
...
llvm-svn: 30975
2006-10-16 16:33:29 +00:00
4c1baf1528
fix some fp condition codes
...
use non trapping comparison instructions
llvm-svn: 30962
2006-10-14 13:42:53 +00:00
5ab3166f74
add FNEGS and FNEGD
...
llvm-svn: 30932
2006-10-13 17:37:35 +00:00
d6050c3149
add SBCS and SUBS
...
llvm-svn: 30930
2006-10-13 17:19:20 +00:00
3874a168d0
implement unordered floating point compares
...
llvm-svn: 30928
2006-10-13 13:14:59 +00:00
8c9422c4b8
mark call adjustments as modifying the SP
...
llvm-svn: 30911
2006-10-12 18:00:26 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
8429e1f6c3
uint <-> double conversion
...
llvm-svn: 30862
2006-10-10 20:38:57 +00:00
b5f1ff336a
add fp sub
...
llvm-svn: 30859
2006-10-10 19:35:01 +00:00
57d109fb08
add double <-> int conversion
...
llvm-svn: 30858
2006-10-10 18:55:14 +00:00
d1a4ea41c9
compare doubles
...
llvm-svn: 30856
2006-10-10 16:33:47 +00:00
d15c892433
initial support for fp compares. Unordered compares not implemented yet
...
llvm-svn: 30854
2006-10-10 12:56:00 +00:00
Evan Cheng