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Add properties to ComplexPattern. 

llvm-svn: 30891
This commit is contained in:
Evan Cheng 2006-10-11 21:03:53 +00:00
parent 2022c79d7f
commit 577ef7694e
6 changed files with 16 additions and 13 deletions
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7
llvm/lib/Target/ARM/ARMInstrInfo.td
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@ -27,12 +27,13 @@ def memri : Operand<iPTR> {
// Define ARM specific addressing mode.
//Addressing Mode 1: data processing operands
def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl]>;
def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
[]>;
//register plus/minus 12 bit offset
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
//register plus scaled register
//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
//===----------------------------------------------------------------------===//
// Instructions

8
llvm/lib/Target/PowerPC/PPCInstrInfo.td
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@ -259,10 +259,10 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
}
// Define PowerPC specific addressing mode.
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.

4
llvm/lib/Target/Sparc/SparcInstrInfo.td
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@ -67,8 +67,8 @@ def SETHIimm : PatLeaf<(imm), [{
}], HI22>;
// Addressing modes.
def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
// Address operands
def MEMrr : Operand<i32> {

4
llvm/lib/Target/TargetSelectionDAG.td
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@ -554,11 +554,13 @@ class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
// RootNodes are the list of possible root nodes of the sub-dags to match.
// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
//
class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = []> {
class ComplexPattern<ValueType ty, int numops, string fn,
list<SDNode> roots = [], list<SDNodeProperty> props = []> {
ValueType Ty = ty;
int NumOperands = numops;
string SelectFunc = fn;
list<SDNode> RootNodes = roots;
list<SDNodeProperty> Properties = props;
}
//===----------------------------------------------------------------------===//

4
llvm/lib/Target/X86/X86InstrInfo.td
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@ -135,9 +135,9 @@ def brtarget : Operand<OtherVT>;
//
// Define X86 specific addressing mode.
def addr : ComplexPattern<iPTR, 4, "SelectAddr", []>;
def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
[add, mul, shl, or, frameindex]>;
[add, mul, shl, or, frameindex], []>;
//===----------------------------------------------------------------------===//
// X86 Instruction Format Definitions.

2
llvm/lib/Target/X86/X86InstrX86-64.td
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@ -38,7 +38,7 @@ def lea64_32mem : Operand<i32> {
// Complex Pattern Definitions...
//
def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
[add, mul, shl, or, frameindex, X86Wrapper]>;
[add, mul, shl, or, frameindex, X86Wrapper], []>;
//===----------------------------------------------------------------------===//
// Instruction templates...