25e62eb63b
Fix a message, patch by Christopher Lamb.
...
llvm-svn: 36264
2007-04-19 18:42:38 +00:00
42cd7253b1
Fix a bug in getFrameRegister.
...
Reported by Raul Herbster.
llvm-svn: 36262
2007-04-19 14:09:38 +00:00
29845cd40d
Fix the spelling of the prefetchnta instruction.
...
llvm-svn: 36256
2007-04-18 14:09:14 +00:00
5118226c6c
Oops. Didn't mean to check in a quick hack.
...
llvm-svn: 36227
2007-04-17 23:33:39 +00:00
598bc0d9a3
dag combiner just got better at pruning bits. This fixes CodeGen/ARM/rev.ll
...
llvm-svn: 36222
2007-04-17 22:39:58 +00:00
2f45bf31c5
Change getAllocatableSet() so it returns allocatable registers for a specific register class.
...
llvm-svn: 36215
2007-04-17 20:23:34 +00:00
9b91d98a30
Add comment
...
llvm-svn: 36213
2007-04-17 19:34:00 +00:00
2509d7547d
add a note
...
llvm-svn: 36203
2007-04-17 18:03:00 +00:00
ff0598de75
rename X86FunctionInfo to X86MachineFunctionInfo to match the header file
...
it is defined in.
llvm-svn: 36196
2007-04-17 17:21:52 +00:00
8b7aab009e
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
...
Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195
2007-04-17 09:20:00 +00:00
2077814c91
Use this nifty Constraints thing and fix the inverted conditional moves
...
llvm-svn: 36191
2007-04-17 04:07:59 +00:00
62a8cbe594
SSE4 is apparently public now.
...
llvm-svn: 36185
2007-04-17 00:02:37 +00:00
6f3a548ff4
In the event that some really old non-Intel or -AMD CPU is encountered...
...
llvm-svn: 36177
2007-04-16 21:59:44 +00:00
da17029218
Before assuming that the original code didn't work for Athlon64, the person who
...
replaced it with a FIXME should have determined what did work. Then he would have
realized that the code was in fact correct, and would have avoided breaking it.
llvm-svn: 36173
2007-04-16 21:48:58 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
19c0217d99
For PR1336:
...
Subtarget option names must be given in lower case in order to be
recognized. Fixes test/CodeGen/Alpha/ctlz.ll
llvm-svn: 36125
2007-04-16 14:06:19 +00:00
e275463e2f
add a note
...
llvm-svn: 36028
2007-04-14 23:06:09 +00:00
b4c610fb89
Silence VC++ warning.
...
llvm-svn: 35975
2007-04-13 22:52:03 +00:00
502c3f48d9
arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.
...
llvm-svn: 35962
2007-04-13 06:50:55 +00:00
9945235b55
Implement review feedback .. don't double search a set.
...
llvm-svn: 35957
2007-04-12 21:57:15 +00:00
0ef2ca8da7
Provide support for intrinsics that lower themselves to a function body.
...
This can happen for intrinsics that are overloaded. In such cases it is
necessary to emit a function prototype before the body of the function
that calls the intrinsic and to ensure we don't emit it multiple times.
llvm-svn: 35954
2007-04-12 21:00:45 +00:00
e6818b2549
Implement Thread Local Storage (TLS) in CBackend.
...
llvm-svn: 35951
2007-04-12 18:42:08 +00:00
2805bce656
Fix mmx paddq, add support for the 'y' register class, though it isn't tested.
...
llvm-svn: 35940
2007-04-12 04:14:49 +00:00
a5fcd24746
Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
...
llvm-svn: 35926
2007-04-11 22:29:46 +00:00
fe926e2960
Fix incorrect fall-throughs in addr mode code. This fixes CodeGen/ARM/arm-negative-stride.ll
...
llvm-svn: 35909
2007-04-11 16:17:12 +00:00
a6aa0319f1
done
...
llvm-svn: 35884
2007-04-11 05:34:00 +00:00
a472f66dd0
For PR1146:
...
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.
llvm-svn: 35877
2007-04-11 02:44:20 +00:00
f099841573
Add support for our first SSSE3 instruction "pmulhrsw".
...
llvm-svn: 35869
2007-04-10 22:10:25 +00:00
d4a9b92a13
new micro optzn
...
llvm-svn: 35867
2007-04-10 21:14:01 +00:00
9b6d69e0c2
restore support for negative strides
...
llvm-svn: 35859
2007-04-10 03:48:29 +00:00
d44e24c896
remove dead target hooks
...
llvm-svn: 35846
2007-04-09 23:33:39 +00:00
808ac93f68
remove some dead hooks
...
llvm-svn: 35845
2007-04-09 23:31:19 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
19ccd6226c
Fix a bug in PPCTargetLowering::isLegalAddressingMode, scales other than 0/1/2
...
are always unsupported.
llvm-svn: 35835
2007-04-09 22:10:05 +00:00
4397363c16
When the number of elements is zero, don't malloc 32GB on 64-bit systems.
...
Fixes unexpected failures on FreeBSD/amd64 of:
CFrontend/2005-09-24-BitFieldCrash.c:
CFrontend/2007-02-04-EmptyStruct.c:
CFrontend/2007-03-26-ZeroWidthBitfield.c:
CodeGen/Generic/2005-10-18-ZeroSizeStackObject.ll:
llvm-svn: 35828
2007-04-09 19:26:30 +00:00
71b79e3d99
For PR1146:
...
Adapt handling of parameter attributes to use the new ParamAttrsList class.
llvm-svn: 35814
2007-04-09 06:17:21 +00:00
7451e4d6a1
move a bunch of register constraints from being handled by
...
getRegClassForInlineAsmConstraint to being handled by
getRegForInlineAsmConstraint. This allows us to let the llvm register allocator
allocate, which gives us better code. For example, X86/2007-01-29-InlineAsm-ir.ll
used to compile to:
_run_init_process:
subl $4, %esp
movl %ebx, (%esp)
xorl %ebx, %ebx
movl $11, %eax
movl %ebx, %ecx
movl %ebx, %edx
# InlineAsm Start
push %ebx ; movl %ebx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
Now we get:
_run_init_process:
xorl %ecx, %ecx
movl $11, %eax
movl %ecx, %edx
# InlineAsm Start
push %ebx ; movl %ecx,%ebx ; int $0x80 ; pop %ebx
# InlineAsm End
llvm-svn: 35804
2007-04-09 05:49:22 +00:00
2b6b4eb471
implement support for CodeGen/X86/inline-asm-x-scalar.ll:test3 - i32/i64 values
...
used with x constraints.
llvm-svn: 35803
2007-04-09 05:31:48 +00:00
590ed5e5b7
implement CodeGen/X86/inline-asm-x-scalar.ll
...
llvm-svn: 35799
2007-04-09 05:11:28 +00:00
e9f516384d
Squelch a warning about mismatch between sign of constant and sign of return
...
type.
llvm-svn: 35674
2007-04-04 22:07:24 +00:00
1e150dedd1
Implement inline asm modifier P.
...
llvm-svn: 35640
2007-04-04 00:13:29 +00:00
bd31f41daa
Typo.
...
llvm-svn: 35639
2007-04-04 00:06:07 +00:00
ac5b650a54
Adding more MMX instructions.
...
llvm-svn: 35638
2007-04-03 23:48:32 +00:00
f79fb5cad0
make a new missing features section
...
llvm-svn: 35637
2007-04-03 23:41:34 +00:00
3c68d4e8ba
Remove unused constant pool entries.
...
llvm-svn: 35635
2007-04-03 23:39:48 +00:00
2640b4a4ab
Updated
...
llvm-svn: 35634
2007-04-03 23:37:20 +00:00
39d8b4db92
Fixed a bug that causes codegen of noop like add r0, r0, #0 .
...
llvm-svn: 35627
2007-04-03 21:31:21 +00:00
23710a7da3
Starting implementation of the ELF32 ABI specification of varargs handling.
...
LowerVASTART emits the right code if the subtarget is ELF32, the other intrinsics
(VAARG, VACOPY and VAEND) are not yet implemented.
llvm-svn: 35625
2007-04-03 13:59:52 +00:00
b3e99a18ee
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
...
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/ ).
Change all ELF tests to ELF32.
llvm-svn: 35624
2007-04-03 12:35:28 +00:00
ab559f6e3c
Addition to the previous commit for getCalleeSavedRegClasses:
...
"The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO."
llvm-svn: 35623
2007-04-03 10:57:49 +00:00
fbfc451ba9
The ELF ABI specifies F1-F8 registers as argument registers for double, not
...
F1-F10. This affects only ELF, not MachO.
llvm-svn: 35622
2007-04-03 10:27:07 +00:00
e8315fe3f5
Inverted logic.
...
llvm-svn: 35619
2007-04-03 06:44:25 +00:00
652c7b2d73
Changed to new MMX_ recipes.
...
llvm-svn: 35617
2007-04-03 06:18:31 +00:00
e7b2a864f2
Add FEMMS and ADDQ. Renamed MMX recipes to prepend the MMX_ to them.
...
llvm-svn: 35616
2007-04-03 06:00:37 +00:00
f742e2fe70
Arm supports negative strides as well, add them. This lets us compile:
...
CodeGen/ARM/arm-negative-stride.ll to:
LBB1_2: @bb
str r1, [r3, -r0, lsl #2 ]
add r0, r0, #1
cmp r0, r2
bne LBB1_2 @bb
llvm-svn: 35609
2007-04-03 00:13:57 +00:00
d13786dd82
fix off by 1 error in displacement computation
...
llvm-svn: 35602
2007-04-02 20:31:06 +00:00
8e168a4f36
fix the CodeGen/ARM/2007-03-13-InstrSched.ll regression: allow IV's with scales
...
to be folded into non-store instructions.
llvm-svn: 35601
2007-04-02 18:51:18 +00:00
6223e83f6d
add support for the 'w' inline asm register class.
...
llvm-svn: 35598
2007-04-02 17:24:08 +00:00
3e21eb7fd7
Fix a bug which caused us to never be able to use signed comparisons for
...
equality comparisons of a constant. This allows us to codegen the 'sintzero'
loop in PR1288 as:
LBB1_1: ;cond_next
li r4, 0
addi r2, r2, 1
stw r4, 0(r3)
addi r3, r3, 4
cmpwi cr0, r2, -1
bne cr0, LBB1_1 ;cond_next
instead of:
LBB1_1: ;cond_next
addi r2, r2, 1
li r4, 0
xoris r5, r2, 65535
stw r4, 0(r3)
addi r3, r3, 4
cmplwi cr0, r5, 65535
bne cr0, LBB1_1 ;cond_next
This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.
llvm-svn: 35590
2007-04-02 05:59:42 +00:00
6be85337b0
- Divides the comparisons in two types: comparisons that only use N and Z
...
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
59a6fa7af6
fix breakage from last night, simplify code.
...
llvm-svn: 35560
2007-04-01 20:49:36 +00:00
17d48a8bc2
Add i16 address mode.
...
llvm-svn: 35551
2007-04-01 08:06:46 +00:00
427ec7fa51
Readme
...
llvm-svn: 35533
2007-03-31 15:05:44 +00:00
a8cc1ebae1
Consistency with native compilers
...
llvm-svn: 35532
2007-03-31 13:11:52 +00:00
b72fcddd23
Fix comment.
...
llvm-svn: 35531
2007-03-31 09:36:12 +00:00
075b4db621
add a note
...
llvm-svn: 35530
2007-03-31 07:06:25 +00:00
afddb2c6f8
Match GCC's MMX calling convention.
...
llvm-svn: 35523
2007-03-31 01:03:53 +00:00
1eb94d973a
implement the new addressing mode description hook.
...
llvm-svn: 35521
2007-03-30 23:15:24 +00:00
2fbcbc16b4
Add MMX calling conventions.
...
llvm-svn: 35489
2007-03-30 00:35:22 +00:00
045414aa8e
New entry.
...
llvm-svn: 35480
2007-03-29 21:40:13 +00:00
cc44b1e743
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
...
llvm-svn: 35479
2007-03-29 21:38:31 +00:00
68e93b7c44
MS C does have inlining after all, just uses _inline instead of inline.
...
llvm-svn: 35467
2007-03-29 17:42:21 +00:00
8f592160c0
Add support for hidden visibility to darwin/arm.
...
llvm-svn: 35448
2007-03-29 07:49:34 +00:00
cc560c93eb
Fix C Backend to generate code that works with Microsoft C for the benefit of
...
front ends that do not depend on the GCC runtime (someday...).
llvm-svn: 35441
2007-03-28 23:08:37 +00:00
4ad38abd40
Made this into a bug report: PR1286
...
llvm-svn: 35439
2007-03-28 19:07:34 +00:00
0ad22563b8
Oops :)
...
llvm-svn: 35438
2007-03-28 18:38:33 +00:00
7522c9d8e1
Don't allow MatchAddress recurse too much. This trims exponential
...
behaviour in some cases.
llvm-svn: 35437
2007-03-28 18:36:33 +00:00
2ba38c8711
add a note
...
llvm-svn: 35435
2007-03-28 18:17:19 +00:00
bcd38852f2
Compile CodeGen/X86/lea-3.ll:test2 to:
...
_test3:
leaq (,%rdi,4), %rax
orq %rdi, %rax
ret
instead of:
_test2:
movq %rdi, %rax
shlq $2, %rax
orq %rdi, %rax
ret
llvm-svn: 35434
2007-03-28 18:12:31 +00:00
a6527d6a61
Dan pointed out that this is done, remove it!
...
llvm-svn: 35430
2007-03-28 17:26:52 +00:00
734077b1f0
First test check-in.
...
llvm-svn: 35429
2007-03-28 17:04:43 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
...
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
2338e21b2b
Remove cruft I put in there...
...
llvm-svn: 35394
2007-03-28 01:02:54 +00:00
c56e4920d2
Fix a problem building llvm-gcc on amd64-unknown-freebsd6.2, due to the
...
system assembler not groking legal instructions like "leal (,%esi,8), %ecx".
llvm-svn: 35393
2007-03-28 00:58:40 +00:00
ad2db4a4cf
Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic.
...
llvm-svn: 35392
2007-03-28 00:57:11 +00:00
999c77f89c
Add the "unpack low packed data" instructions. This should be the last of
...
the MMX instructions that are needed...
llvm-svn: 35389
2007-03-27 21:20:36 +00:00
6dff51ae65
Fix so that pandn is emitted instead of an xor/and combo. Add integer
...
comparison operators.
llvm-svn: 35385
2007-03-27 20:22:40 +00:00
682baf2dda
"The C standards do say that "char" may either be a "signed char" or "unsigned
...
char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php
llvm-svn: 35382
2007-03-27 16:33:08 +00:00
143b0dff31
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
...
llvm-svn: 35381
2007-03-27 16:19:21 +00:00
7dbbd00b06
findRegisterUseOperand() changed.
...
llvm-svn: 35366
2007-03-26 22:41:48 +00:00
158f6092a2
Promote to v1i64 type...
...
llvm-svn: 35353
2007-03-26 08:03:33 +00:00
48a24419bf
Updated.
...
llvm-svn: 35352
2007-03-26 07:55:58 +00:00
98d2104c6f
Add support for the v1i64 type. This makes better code for this:
...
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
llvm-svn: 35351
2007-03-26 07:53:08 +00:00
e8ac2fce97
Fix authorship
...
llvm-svn: 35337
2007-03-25 13:44:26 +00:00
26ad3e7191
add a note
...
llvm-svn: 35334
2007-03-25 05:10:46 +00:00
9c9e2f1af2
add a note
...
llvm-svn: 35330
2007-03-25 04:46:28 +00:00
8810241ebc
Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll
...
llvm-svn: 35329
2007-03-25 04:44:03 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
927f30da08
Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers.
...
llvm-svn: 35320
2007-03-25 02:01:03 +00:00
03a643aa69
enforce the proper range for the i386 N constraint.
...
llvm-svn: 35319
2007-03-25 01:57:35 +00:00
c8ddca703d
Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
...
llvm-svn: 35318
2007-03-25 01:44:57 +00:00
43cab75914
add a bad case evan though of.
...
llvm-svn: 35296
2007-03-24 06:01:32 +00:00
8aae2d7e1c
Autodetect MMX & SSE stuff for AMD processors
...
llvm-svn: 35292
2007-03-23 23:46:48 +00:00
871c77cda1
PR1260:
...
Add final support to get the QT example to compile.
llvm-svn: 35290
2007-03-23 22:35:46 +00:00
7c17fbc5b7
We generate a shufflevector instruction, so we don't need the builtin
...
intrinsic.
llvm-svn: 35269
2007-03-22 20:29:26 +00:00
d551a18783
Support added for shifts and unpacking MMX instructions.
...
llvm-svn: 35266
2007-03-22 18:42:45 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
4ad4bcdc2d
Add TODO list for MSIL backend
...
llvm-svn: 35244
2007-03-21 21:48:59 +00:00
aa3090d815
Let the new backend begin!
...
llvm-svn: 35242
2007-03-21 21:38:25 +00:00
a827d03154
add generation of unnecessary push/pop around calls
...
llvm-svn: 35241
2007-03-21 21:16:39 +00:00
4ea5217880
Protect R31's frame offset from being used by callee-saved registers, when R31
...
is the frame pointer.
llvm-svn: 35233
2007-03-21 16:44:14 +00:00
61eee86487
Mark re-materializable instructions.
...
llvm-svn: 35230
2007-03-21 00:16:56 +00:00
cba9538499
Updated.
...
llvm-svn: 35229
2007-03-20 22:32:39 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
a88c4a74f3
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
...
mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
9e7b838469
Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool.
...
llvm-svn: 35207
2007-03-20 08:11:30 +00:00
39eb62ea3b
New entry.
...
llvm-svn: 35206
2007-03-20 08:10:17 +00:00
61f39d186c
Added MRegisterInfo hook to re-materialize an instruction.
...
llvm-svn: 35205
2007-03-20 08:09:38 +00:00
3e1d917e80
Two changes:
...
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2 , #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
llvm-svn: 35204
2007-03-20 06:08:29 +00:00
f806e1cdbc
fix indentation
...
llvm-svn: 35202
2007-03-20 02:25:53 +00:00
8447d34903
fix obvious comment bug
...
llvm-svn: 35196
2007-03-20 00:30:56 +00:00
9bb01c9f4f
Fix naming inconsistencies.
...
llvm-svn: 35163
2007-03-19 07:48:02 +00:00
ee2763f76f
Special LDR instructions to load from non-pc-relative constantpools. These are
...
rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
5be3e09a30
Constant generation instructions are re-materializable.
...
llvm-svn: 35161
2007-03-19 07:09:02 +00:00
461c964d3d
Added isReMaterializable.
...
llvm-svn: 35160
2007-03-19 06:22:07 +00:00
f01f87bc63
fix a warning
...
llvm-svn: 35152
2007-03-19 00:39:32 +00:00
9b3e2b4ad9
minor updates
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llvm-svn: 35143
2007-03-18 22:41:33 +00:00
f764441977
This is implemented. We now generate:
...
entry:
icmp ugt i32 %x, 4 ; <i1>:0 [#uses=1]
br i1 %0, label %cond_true, label %cond_false
cond_true: ; preds = %entry
%tmp1 = tail call i32 (...)* @bar( i32 12 ) ; <i32> [#uses=0]
ret void
cond_false: ; preds = %entry
switch i32 %x, label %cond_true15 [
i32 4, label %cond_true3
i32 3, label %cond_true7
i32 2, label %cond_true11
i32 0, label %cond_false17
]
...
llvm-svn: 35142
2007-03-18 14:37:20 +00:00
b38c2ec89c
Support 'I' inline asm constraint.
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llvm-svn: 35129
2007-03-17 00:13:28 +00:00
25d4052af6
Only ARMv6 has BSWAP.
...
Fix MultiSource/Applications/aha test.
llvm-svn: 35128
2007-03-16 22:54:16 +00:00
144b8bbf17
And now support for MMX logical operations.
...
llvm-svn: 35125
2007-03-16 09:44:46 +00:00
0e34d6af6b
Added isLegalAddressExpression(). Only allows X +/- C for now.
...
llvm-svn: 35122
2007-03-16 08:43:56 +00:00
e31034125c
Multiplication support for MMX.
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llvm-svn: 35118
2007-03-15 21:24:36 +00:00
a1779b9739
Under X86-64 large code model, do not emit 32-bit pc relative calls.
...
llvm-svn: 35108
2007-03-14 22:11:11 +00:00
71face25ef
Notes about codegen issues.
...
llvm-svn: 35107
2007-03-14 21:03:53 +00:00
e278f30a52
Clean up.
...
llvm-svn: 35105
2007-03-14 20:20:19 +00:00
eb76f7c6fd
Oops.
...
llvm-svn: 35104
2007-03-14 19:44:58 +00:00
dda4c32db3
X86-64 JIT is in large code model. Need stubs for direct calls.
...
llvm-svn: 35097
2007-03-14 10:51:55 +00:00
386dfc9251
x86-64 JIT stub codegen.
...
llvm-svn: 35096
2007-03-14 10:48:08 +00:00
e1a95206e3
Preliminary support for X86-64 JIT stub codegen.
...
llvm-svn: 35095
2007-03-14 10:44:30 +00:00
72a8bcf238
AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2 ]
...
llvm-svn: 35088
2007-03-13 21:05:54 +00:00
507eefa757
Zero is always a legal AM immediate.
...
llvm-svn: 35087
2007-03-13 20:37:59 +00:00
7aad92868c
Stack and register alignment of call arguments in the ELF ABI
...
llvm-svn: 35083
2007-03-13 15:02:46 +00:00
818242bbaf
Implement getTargetLowering() or else LSR won't be using ARM specific hooks.
...
llvm-svn: 35077
2007-03-13 01:20:42 +00:00
2150b9286f
Updated TargetLowering LSR addressing mode hooks for ARM and Thumb.
...
llvm-svn: 35075
2007-03-12 23:30:29 +00:00
b9dce9db85
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35074
2007-03-12 23:29:01 +00:00
3ab7ea7965
More flexible TargetLowering LSR hooks for testing whether an immediate is
...
a legal target address immediate or scale.
llvm-svn: 35073
2007-03-12 23:28:50 +00:00
57f261b13a
Stupid bug: SSE2 supports v2i64 add / sub.
...
llvm-svn: 35070
2007-03-12 22:58:52 +00:00
e9b81f5366
Adding more arithmetic operators to MMX. This is an almost exact copy of
...
the addition. Please let me know if you have suggestions.
llvm-svn: 35055
2007-03-10 09:57:05 +00:00
09663aeac7
Minor stuff.
...
llvm-svn: 35049
2007-03-09 19:46:06 +00:00
31ef0ab7cf
Add comments about LSR / ARM.
...
llvm-svn: 35048
2007-03-09 19:35:33 +00:00
603f3094eb
Unfinished work and ideas related to register scavenger.
...
llvm-svn: 35047
2007-03-09 19:34:51 +00:00
368faf9acd
apply comments from review of last patch
...
llvm-svn: 35045
2007-03-09 19:18:59 +00:00
af0cff2671
Add some observations from CoreGraphics benchmark. Remove register
...
scavenging todo item, since it is now implemented.
llvm-svn: 35044
2007-03-09 17:58:17 +00:00
ea28fc5dc4
Implement inline asm modifier c.
...
llvm-svn: 35035
2007-03-08 22:42:46 +00:00
6092ce25cf
Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that
...
moves, loads, etc. are recognized.
llvm-svn: 35031
2007-03-08 22:09:11 +00:00
63170b6959
Fix a typo.
...
llvm-svn: 35030
2007-03-08 21:59:30 +00:00
ddf082082c
Putting more constants which do not contain relocations into .literal{4|8|16}
...
llvm-svn: 35026
2007-03-08 08:31:54 +00:00
e94a2f8026
Change register allocation order to Dale's suggestion.
...
llvm-svn: 35021
2007-03-08 02:56:40 +00:00
977195e912
Bug fix. Not advancing the register scavenger iterator correctly.
...
llvm-svn: 35020
2007-03-08 02:55:08 +00:00
d918477ac3
For Darwin, put constant data into .const, .const_data, .literal{4|8|16}
...
sections.
llvm-svn: 35017
2007-03-08 01:25:25 +00:00
13a1d96963
Put constant data to .const, .const_data, .literal{4|8|16} sections.
...
llvm-svn: 35016
2007-03-08 01:07:07 +00:00
58aeb9c444
Add ReadOnlySection directive.
...
llvm-svn: 35015
2007-03-08 01:00:38 +00:00
f030f2d628
Only safe to use a call-clobbered or spilled callee-saved register as scratch register.
...
llvm-svn: 35010
2007-03-07 20:30:36 +00:00
6d8211c0ac
Remove useless pattern fragments.
...
llvm-svn: 35009
2007-03-07 18:23:09 +00:00
ed4b303c10
Refactoring of formal parameter flags. Enable properly use of
...
zext/sext/aext stuff.
llvm-svn: 35008
2007-03-07 16:25:09 +00:00
97905b4027
Properly support v8i8 and v4i16 types. It now converts them to v2i32 for
...
load and stores.
llvm-svn: 35002
2007-03-07 05:43:18 +00:00
942fda027f
Fix DWARF debugging information on x86/Linux and (hopefully)
...
Mingw32/Cygwin targets. This fixes PR978
llvm-svn: 35000
2007-03-07 02:47:57 +00:00
17cdad0687
ARM always use register scavenger. No longer reserves R12.
...
llvm-svn: 34999
2007-03-07 02:46:23 +00:00
2818fdd019
Fix some brittle code. Watch out for cases where register scavenger is pointing to deleted instructions.
...
llvm-svn: 34998
2007-03-07 02:38:05 +00:00
67038e7a8b
Fix one more Thumb eliminateFrameIndex bug.
...
llvm-svn: 34990
2007-03-07 00:12:18 +00:00
5ed781b0db
Register scavenging is now on by default for ARM.
...
llvm-svn: 34987
2007-03-06 22:02:53 +00:00
41bc2fd242
Make load / store optimizer use register scavenger.
...
llvm-svn: 34986
2007-03-06 21:59:20 +00:00
bbd25984b7
Add LOAD/STORE support for MMX.
...
llvm-svn: 34978
2007-03-06 18:53:42 +00:00
d28de6700b
Code clean up. Prepare to use register scavenger.
...
llvm-svn: 34976
2007-03-06 18:02:41 +00:00
8b8cac289b
Minor interface change.
...
llvm-svn: 34967
2007-03-06 10:05:14 +00:00
4783ae8ac1
Scavenge a register using the register scavenger when needed.
...
llvm-svn: 34966
2007-03-06 10:03:56 +00:00
e7ec3bc7bc
Use new SDIselParamAttr enumeration. This removes "magick" constants
...
from formal attributes' flags processing.
llvm-svn: 34963
2007-03-06 08:12:33 +00:00
4f2e4e0f92
Switch PPC return lower to use an autogenerated CC description.
...
llvm-svn: 34940
2007-03-06 00:59:59 +00:00
b1c86b49ea
Add the emms intrinsic for MMX support.
...
llvm-svn: 34938
2007-03-05 23:09:45 +00:00
f10769dda7
Use init_array/fini_array sections for static contructors/destructors when the ABI is AAPCS.
...
Fix SingleSource/Regression/C/ConstructorDestructorAttributes test on arm-linux-gnueabi.
llvm-svn: 34931
2007-03-05 17:59:58 +00:00
b622c11f77
Unbreak VC++ build.
...
llvm-svn: 34917
2007-03-05 00:00:42 +00:00
d647f92a14
add missing braces
...
llvm-svn: 34905
2007-03-04 06:13:52 +00:00
1f87660d29
Make sure that when we store a value it is masked to its correct bit
...
width. This helps CBE work with non-standard integer bit widths.
llvm-svn: 34885
2007-03-03 16:33:33 +00:00
e6049c2f08
Emit low/high immediate loads properly for Linux/PPC.
...
llvm-svn: 34871
2007-03-03 05:29:51 +00:00
deaea25eb9
X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }.
...
llvm-svn: 34857
2007-03-02 23:16:35 +00:00
57af2a4f3b
Simplify things
...
llvm-svn: 34849
2007-03-02 21:50:27 +00:00
9c7e5e365d
argument lowering should copy from the vreg shadows of live-in arguments
...
passed in registers, not directly from the pregs themselves.
llvm-svn: 34838
2007-03-02 05:12:29 +00:00
fc2f52128a
add a note
...
llvm-svn: 34837
2007-03-02 05:04:52 +00:00
32bc81341b
eliminate unnecessary reset of SP in epilog on darwin
...
llvm-svn: 34824
2007-03-02 01:17:17 +00:00
df30e2a68b
Wrap a long line.
...
llvm-svn: 34799
2007-03-01 19:48:16 +00:00
af8be4458f
Ensure that fastcall'ed function is correctly mangled & stack is
...
properly aligned
llvm-svn: 34788
2007-03-01 16:29:22 +00:00
75ab9799df
Implemented the frameaddress intrinsic for PPC.
...
llvm-svn: 34787
2007-03-01 13:11:38 +00:00
2c0fd3ee4c
Use a spilled free callee-saved register as scratch register.
...
llvm-svn: 34785
2007-03-01 08:57:52 +00:00
6f059e3e0a
- Track which callee-saved registers are spilled.
...
- Some code clean up.
llvm-svn: 34783
2007-03-01 08:26:31 +00:00
677bb3b460
Switch from std::vector<bool> to BitVector.
...
llvm-svn: 34781
2007-03-01 07:52:44 +00:00
65c75b57d4
Get rid of verboten <iostream> include.
...
llvm-svn: 34777
2007-03-01 06:05:39 +00:00
962fa8eb9a
Changes requested in review of last pass. Also pulled isThumb into a
...
member, instead of resetting in every function that uses it.
llvm-svn: 34764
2007-02-28 23:20:38 +00:00
f6ca943638
Doh. ARM::PC is obvious a reserved register.
...
llvm-svn: 34763
2007-02-28 23:12:34 +00:00
440995bd9a
Add intelligence about where to break large blocks.
...
llvm-svn: 34755
2007-02-28 18:41:23 +00:00
Chris Lattner