Support added for shifts and unpacking MMX instructions.
llvm-svn: 35266
This commit is contained in:
Bill Wendling
parent
dcb291faa4
commit
d551a18783
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@ -585,3 +585,41 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_v2i32_ty, llvm_v4i16_ty,
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llvm_v4i16_ty], [IntrNoMem]>;
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}
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// Integer shift ops.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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// Shift left logical
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def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">,
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Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">,
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Intrinsic<[llvm_v8i8_ty, llvm_v8i8_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">,
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Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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}
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// Vector pack/unpack ops.
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_mmx_punpckh_dq : GCCBuiltin<"__builtin_ia32_punpckhdq">,
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Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
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llvm_v2i32_ty], [IntrNoMem]>;
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}
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@ -0,0 +1,59 @@
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//===---------------------------------------------------------------------===//
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// Random ideas for the X86 backend: MMX-specific stuff.
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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We should compile
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#include <mmintrin.h>
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extern __m64 C;
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void baz(__v2si *A, __v2si *B)
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{
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*A = __builtin_ia32_psllq(*B, C);
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_mm_empty();
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}
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to:
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.globl _baz
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_baz:
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call L3
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"L00000000001$pb":
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L3:
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popl %ecx
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subl $12, %esp
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movl 20(%esp), %eax
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movq (%eax), %mm0
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movl L_C$non_lazy_ptr-"L00000000001$pb"(%ecx), %eax
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movq (%eax), %mm1
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movl 16(%esp), %eax
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psllq %mm1, %mm0
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movq %mm0, (%eax)
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emms
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addl $12, %esp
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ret
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not:
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_baz:
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subl $12, %esp
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call "L1$pb"
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"L1$pb":
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popl %eax
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movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
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movl (%eax), %ecx
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movl %ecx, (%esp)
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movl 4(%eax), %eax
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movl %eax, 4(%esp)
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movl 20(%esp), %eax
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movq (%eax), %mm0
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movq (%esp), %mm1
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psllq %mm1, %mm0
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movl 16(%esp), %eax
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movq %mm0, (%eax)
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emms
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addl $12, %esp
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ret
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@ -571,4 +571,44 @@ swizzle:
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movaps %xmm0, (%eax)
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ret
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//===---------------------------------------------------------------------===//
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We should compile this:
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#include <xmmintrin.h>
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void foo(__m128i *A, __m128i *B) {
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*A = _mm_sll_epi16 (*A, *B);
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}
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to:
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_foo:
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subl $12, %esp
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movl 16(%esp), %edx
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movl 20(%esp), %eax
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movdqa (%edx), %xmm1
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movdqa (%eax), %xmm0
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psllw %xmm0, %xmm1
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movdqa %xmm1, (%edx)
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addl $12, %esp
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ret
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not:
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_foo:
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movl 8(%esp), %eax
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movdqa (%eax), %xmm0
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#IMPLICIT_DEF %eax
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pinsrw $2, %eax, %xmm0
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xorl %ecx, %ecx
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pinsrw $3, %ecx, %xmm0
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pinsrw $4, %eax, %xmm0
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pinsrw $5, %ecx, %xmm0
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pinsrw $6, %eax, %xmm0
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pinsrw $7, %ecx, %xmm0
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movl 4(%esp), %eax
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movdqa (%eax), %xmm1
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psllw %xmm0, %xmm1
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movdqa %xmm1, (%eax)
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ret
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@ -355,6 +355,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
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setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
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}
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if (Subtarget->hasSSE1()) {
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@ -2312,7 +2316,7 @@ static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
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return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
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}
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/// LowerBuildVectorv16i8 - Custom lower build_vector of v8i16.
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/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
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///
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static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
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unsigned NumNonZero, unsigned NumZero,
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@ -44,6 +44,10 @@ def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
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def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
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def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
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def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
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def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
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//===----------------------------------------------------------------------===//
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// MMX Multiclasses
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//===----------------------------------------------------------------------===//
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@ -94,13 +98,28 @@ let isTwoAddress = 1 in {
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[(set VR64:$dst,
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(OpNode VR64:$src1,(loadv2i32 addr:$src2)))]>;
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}
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multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
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string OpcodeStr, Intrinsic IntId> {
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def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
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def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (loadv2i32 addr:$src2))))]>;
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def ri : MMXIi8<opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(scalar_to_vector (i32 imm:$src2))))]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// MMX EMMS Instruction
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//===----------------------------------------------------------------------===//
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def EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
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def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
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//===----------------------------------------------------------------------===//
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// MMX Scalar Instructions
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@ -132,6 +151,53 @@ defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
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defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw" , int_x86_mmx_pmulh_w , 1>;
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defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
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def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHMask(N);
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}]>;
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let isTwoAddress = 1 in {
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def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhbw {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v8i8 (vector_shuffle VR64:$src1,
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(bc_v8i8 (loadv2i32 addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhwd {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle VR64:$src1,
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(bc_v4i16 (loadv2i32 addr:$src2)),
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, VR64:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
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MMX_UNPCKH_shuffle_mask)))]>;
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def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
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(ops VR64:$dst, VR64:$src1, i64mem:$src2),
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"punpckhdq {$src2, $dst|$dst, $src2}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle VR64:$src1,
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(loadv2i32 addr:$src2),
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MMX_UNPCKH_shuffle_mask)))]>;
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}
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_v2i32<0xDB, "pand", and, 1>;
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defm MMX_POR : MMXI_binop_rm_v2i32<0xEB, "por" , or, 1>;
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@ -150,6 +216,26 @@ let isTwoAddress = 1 in {
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(load addr:$src2))))]>;
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}
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// Shift Instructions
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defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
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int_x86_mmx_psrl_w>;
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defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
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int_x86_mmx_psrl_d>;
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defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
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int_x86_mmx_psrl_q>;
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defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
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int_x86_mmx_psll_w>;
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defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
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int_x86_mmx_psll_d>;
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defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
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int_x86_mmx_psll_q>;
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defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
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int_x86_mmx_psra_w>;
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defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
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int_x86_mmx_psra_d>;
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// Move Instructions
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def MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
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"movd {$src, $dst|$dst, $src}", []>;
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@ -225,3 +311,23 @@ def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
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def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
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def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
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def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
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// Splat v2i32
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let AddedComplexity = 10 in {
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def : Pat<(vector_shuffle (v2i32 VR64:$src), (undef),
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MMX_UNPCKH_shuffle_mask:$sm),
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(MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
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}
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// FIXME: Temporary workaround because 2-wide shuffle is broken.
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def : Pat<(int_x86_mmx_punpckh_dq VR64:$src1, VR64:$src2),
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(v2i32 (MMX_PUNPCKHDQrr VR64:$src1, VR64:$src2))>;
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def : Pat<(int_x86_mmx_punpckh_dq VR64:$src1, (load addr:$src2)),
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(v2i32 (MMX_PUNPCKHDQrm VR64:$src1, addr:$src2))>;
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def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
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// Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower 8 or
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// 16-bits matter.
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def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
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def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MOVD64rr GR32:$src)>;
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