abejgonzalez
858ea6a4f3
Deprecate Dromajo, use Cospike
2023-08-30 17:54:27 -07:00
abejgonzalez
05dbb2f0ce
Point to Chipyard sbt-launch.jar
2023-08-30 17:39:35 -07:00
Sagar Karandikar
d1bddb4ea7
u200 support test
2023-07-01 20:12:25 -07:00
Sagar Karandikar
cd69214afd
Merge remote-tracking branch 'origin/main' into nitefury_ii
2023-06-05 11:44:40 -07:00
Sagar Karandikar
676bd99f50
Merge remote-tracking branch 'origin/main' into nitefury_ii
2023-06-02 08:07:52 -07:00
Abraham Gonzalez
fafd214efc
Touch *.jar assembly files
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If the *.jar is up-to-date SBT assembly will not touch the *.jar file causing downstream make recipes to not have an updated timestamp for the *.jar file.
2023-06-02 00:35:28 -07:00
abejgonzalez
dbbb671236
Merge remote-tracking branch 'origin/misc-fixes' into vlog-as-top
2023-05-31 14:30:21 -07:00
abejgonzalez
ce4c0b4e80
Update TARGET_CP when running non-firesim projects
2023-05-31 13:58:14 -07:00
abejgonzalez
8aa3cfa6bc
Fix scala-build for other non-firesim projects
2023-05-31 12:06:31 -07:00
abejgonzalez
ee0ed548b1
Align SBT_OPTS w/ CY | Rename JVM_MEMORY -> JAVA_HEAP_SIZE
2023-05-31 11:13:33 -07:00
abejgonzalez
d279c46345
Merge remote-tracking branch 'origin/main' into vlog-as-top
2023-05-30 20:24:29 -07:00
Abraham Gonzalez
14c6fc9843
Merge pull request #1529 from firesim/cy-fs-fat-jar
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Use fat jar to reduce SBT invocations instead of cached classpath
2023-05-30 20:23:53 -07:00
abejgonzalez
63199b38b7
Small fixes
2023-05-29 17:03:02 -07:00
abejgonzalez
c48caf3952
Merge remote-tracking branch 'origin/use-fat-jars' into cy-fs-fat-jar
2023-05-29 16:05:43 -07:00
abejgonzalez
46553cd7a8
Skip dpi.cc in lint | More use ssh config in CI
2023-05-29 15:43:08 -07:00
abejgonzalez
41a354fb11
Use SSH config in manager | Cpp-Lint fixes
2023-05-28 11:01:04 -07:00
abejgonzalez
33b2be5792
Fix unittest makefile
2023-05-26 17:37:29 -07:00
abejgonzalez
938351f426
Rework GG comp. to support Vlog top + Xcelium
2023-05-26 01:16:22 -07:00
Sagar Karandikar
d1f5da3459
nitefury working firesim buildbitstream
2023-05-20 17:44:44 -07:00
Sagar Karandikar
4f10f91555
Merge remote-tracking branch 'origin/main' into vcu118
2023-05-10 11:48:44 -07:00
Jerry Zhao
966e09907c
Merge pull request #1500 from firesim/renameserial
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Rename SerialBridge to TSIBridge
2023-05-10 11:37:26 -07:00
Abraham Gonzalez
0c1a7a6339
Merge pull request #1471 from firesim/bump-verilator
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Bump Verilator to 5.006
2023-05-09 13:12:44 -07:00
Jerry Zhao
73ad11a969
Fix tsibridge cc/h linting
2023-05-09 10:47:49 -07:00
Sagar Karandikar
a4a7811298
Merge remote-tracking branch 'origin/ntnu-integration' into vcu118
2023-05-06 18:39:04 -07:00
abejgonzalez
fa882bc8ad
Fix Makefile paths
2023-05-06 17:30:34 -07:00
Sagar Karandikar
d6de4ab565
vcu118 support throughout firesim
2023-05-06 17:09:18 -07:00
abejgonzalez
f6fc4ccfec
Intermediate changes [ci skip]
2023-05-04 23:35:56 -07:00
abejgonzalez
c231ca15f4
First attempt at bare Xilinx U250 support
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Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: Björn Gottschall <info@gottschall.no>
Co-authored-by: David Metz <david.c.metz@ntnu.no>
2023-05-03 01:07:15 -07:00
abejgonzalez
18d68946f3
Change to C++20, Fix clock gating in Verilator
2023-03-18 12:39:44 -07:00
abejgonzalez
cbfc9a6430
Merge remote-tracking branch 'origin/main' into local-fpga-docs
2023-03-11 15:49:21 -08:00
abejgonzalez
69e428f010
Local .ivy2/.sbt
2023-03-05 22:39:45 -08:00
abejgonzalez
d826776d6c
Update docs w/ fixes
2023-03-05 17:40:33 -08:00
abejgonzalez
2f13158e0e
Initial support for fat jars
2023-03-03 17:17:16 -08:00
abejgonzalez
31049aae1e
Remove SBT thin client
2023-03-02 23:18:28 -08:00
Nandor Licker
e0569ff124
Fix replace-rtl ordering problem ( #1444 )
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Not all sub-rules build the directory and replace-rtl failed if trying to copy the driver first.
2023-02-28 17:01:46 +02:00
Nandor Licker
0755382dae
Extends tests to work with post-synth RTL ( #1439 )
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Includes improvements to post-synth simulations:
- Added a `QUICK` strategy which tries to get Vivado to run fast, yet still helps us reproduce failures
- Limited Vivado to 1 thread to mitigate flakyness from parallel synthesis
- The harness now explicitly waits for GSR
- Integrated post-synth metasims with the harness. Setting `TEST_DISABLE_VIVADO=1` in the environment disables these tests even if Vivado is available.
Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-27 18:20:01 +02:00
Nandor Licker
fc759f29f1
VCS post-synthesis RTL simulators ( #1438 )
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This PR adds make rules to get the post-synth RTL out of vivado and build a VCS simulator out of it.
On VCS, a 150ns startup delay is hard-wired on all simulation modes to yield identical waveforms.
The delay is required to initialize vivado gate-level libraries.
Co-authored-by: Nandor Licker <nandorl@sifive.com>
2023-02-24 08:06:50 +02:00
Nandor Licker
797e6e41bc
Introduced a full verilator/vcs/debug matrix ( #1435 )
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This PR moves the paramterization of test harnesses to the toplevel.
Slightly re-wrote tests to avoid duplication of running logic.
2023-02-19 11:31:03 +00:00
Benjamin Morse
bec25aaf19
Tests for existing TracerV bridge including trigger modes ( #1426 )
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* Tests for mode 0,1,2
* Test for mode 3 disabled until Issue #1428 is resolved
2023-02-09 11:40:04 -08:00
Abraham Gonzalez
9d3462ed13
Merge pull request #1392 from firesim/scala213
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Bump to latest rocket-chip/scala2.13
2023-02-01 14:30:09 -08:00
Nandor Licker
2889818e7d
Removed the compiler-generated runtime config ( #1422 )
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The default arguments to FASED memory models are now passed alongside other FASED bridge arguments.
These defaults can be overriden by other args passed to the bridge driver or disabled when the raw hardware configuration is requested.
The manager can still pass an optional runtime config to the design to override arguments.
2023-02-01 19:19:00 +02:00
Nandor Licker
4d1876334e
Introduced a unique main to the simulation. ( #1368 )
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The main method centralizes more of the lifecycle of a simulation.
2023-02-01 10:40:08 +02:00
Jerry Zhao
2a5f0cfe70
Revert changing testOnly behavior
2023-01-30 23:30:17 -08:00
Jerry Zhao
96ef6200fe
Bump chipyard.mk to scala 2.13
2023-01-27 13:52:18 -08:00
Jerry Zhao
d384fc52bc
Fix testOnly rule
2023-01-27 13:52:18 -08:00
abejgonzalez
240875234d
Fix Vitis driver compile | Fix CY-as-top issues
2023-01-27 18:00:48 +00:00
Nandor Licker
6d39766d6d
Fix incremental builds triggered by scala changes ( #1408 )
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Fixed the DRY'd grep pattern. Incremental builds should work now.
2023-01-26 09:56:13 -08:00
Benjamin Morse
a513c0ef58
Add scalaFix ( #1393 )
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* adding scalaFix to the projecting, using two make targets, `scala-lint` and `scala-lint-check`
* adding documentation
Co-authored-by: David Biancolin <david.biancolin@sifive.com>
2023-01-25 10:34:10 -08:00
Nandor Licker
c2204d6593
Added a bridge registry to own all bridge instances ( #1369 )
2023-01-24 23:08:59 +00:00
Nandor Licker
70f8996484
Applied clang-tidy fixes ( #1402 )
2023-01-24 18:53:24 +00:00