Feng Wang
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7e41738078
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implement 2-input LUT mapping. Decomposition failed!
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2020-02-27 00:28:59 +08:00 |
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Feng Wang
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e1848ade08
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Merge branch 'master' of https://github.com/yzwangfeng/MOLM
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2020-02-27 00:17:54 +08:00 |
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Feng Wang
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44a460cdac
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change library
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2020-02-27 00:17:43 +08:00 |
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PKU-ZLR
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ea91c35dba
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Upload Circuit.h
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2020-02-26 23:13:18 +08:00 |
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PKU-ZLR
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64da250dd2
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Upload MAIN.CPP
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2020-02-26 23:12:28 +08:00 |
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Feng Wang
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5f62f443bb
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2LUT.lutlib has a bug
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2020-02-26 15:13:14 +08:00 |
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PKU-ZLR
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534fb1c758
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Add files via upload
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2020-02-25 11:37:29 +08:00 |
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PKU-ZLR
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74a3018d86
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Add files via upload
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2020-02-25 11:36:04 +08:00 |
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Feng Wang
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fb2543d92d
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add LUT2 mapping
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2020-02-24 11:52:54 +08:00 |
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PKU-ZLR
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29462a84de
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Add iteration process
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2020-02-23 18:04:35 +08:00 |
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Feng Wang
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2a6ccb69cb
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add toy examples
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2020-02-19 10:21:27 +08:00 |
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Feng Wang
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ee820e8ff2
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ignore
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2020-01-07 13:33:32 +08:00 |
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Feng Wang
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9941ed82ec
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print information into .csv
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2019-12-16 21:24:09 +08:00 |
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Feng Wang
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a65c0e07e2
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update suc
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2019-12-15 11:38:37 +08:00 |
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PKU-ZLR
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6e69abdc8d
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Upload Match
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2019-12-15 03:10:08 +08:00 |
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Feng Wang
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dbda625f4e
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to debug
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2019-12-11 21:41:55 +08:00 |
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Feng Wang
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48788c8c05
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lut decomposition
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2019-12-10 19:34:44 +08:00 |
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Feng Wang
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e3e1348513
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annotation
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2019-12-08 15:36:23 +08:00 |
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Feng Wang
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90f46fa8d9
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recover read_blif
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2019-12-08 15:12:38 +08:00 |
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Feng Wang
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f2d8140a77
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add 2INPUT.genlib
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2019-12-08 15:03:29 +08:00 |
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PKU-ZLR
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e138645b4e
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Upload graph Match
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2019-12-07 12:57:48 +08:00 |
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PKU-ZLR
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5ba9936da3
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Add files via upload
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2019-12-07 12:57:00 +08:00 |
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Feng Wang
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26e5f2e999
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fix read_blif bugs
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2019-12-05 10:30:55 +08:00 |
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Feng Wang
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c4f46f5886
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abc_equivalence_check function debug
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2019-12-04 21:48:24 +08:00 |
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Feng Wang
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603967539d
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update abc function call
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2019-12-04 21:26:52 +08:00 |
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PKU-ZLR
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2accc3584b
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2 outputs upload
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2019-11-30 01:57:50 +08:00 |
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PKU-ZLR
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3b2c581ca9
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upload Circuit.h
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2019-11-30 01:56:42 +08:00 |
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PKU-ZLR
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413162d602
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Upload Circuit.h
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2019-11-02 14:14:35 +08:00 |
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PKU-ZLR
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0eeed0d95f
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Update MAIN and Circuit
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2019-11-02 14:11:12 +08:00 |
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PKU-ZLR
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dfec04e653
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Update MAIN.cpp
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2019-10-29 20:46:10 +08:00 |
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Feng Wang
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f5f308d1e8
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ignore the result folder and the tmp file
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2019-10-23 21:16:35 +08:00 |
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Feng Wang
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55dbe382f6
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record our area and abc area
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2019-10-23 21:13:43 +08:00 |
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Feng Wang
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4658018803
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lutpack debug
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2019-10-23 13:31:38 +08:00 |
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PKU-ZLR
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b6e451b5ed
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Upload ISCAS85 result
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2019-10-23 00:25:22 +08:00 |
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PKU-ZLR
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ee18b20640
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Upload MAIN
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2019-10-23 00:21:31 +08:00 |
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PKU-ZLR
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1635288fbd
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upload Circuit.h
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2019-10-23 00:19:29 +08:00 |
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Feng Wang
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48acd5aa13
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fix main.cpp
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2019-10-20 21:07:25 +08:00 |
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Feng Wang
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b572c835e3
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update the result of abc lut mapping command "lutpack"
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2019-10-20 21:06:08 +08:00 |
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PKU-ZLR
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b17494921d
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Add files via upload
Update MAIN
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2019-10-18 00:26:20 +08:00 |
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PKU-ZLR
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3d2f246214
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Update MAIN.cpp
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2019-10-18 00:24:37 +08:00 |
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Feng Wang
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f0b63f08ba
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add ISCAS89 benchmarks
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2019-10-09 15:16:52 +08:00 |
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Feng Wang
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71c53b0ad8
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Add ISCAS89 benchmarks
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2019-10-09 14:09:57 +08:00 |
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Feng Wang
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f8539e8f9a
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move circuit.h into the include folder
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2019-10-08 19:28:53 +08:00 |
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PKU-ZLR
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3d9be14b65
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Add files via upload
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2019-10-08 15:54:08 +08:00 |
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PKU-ZLR
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2682f6f722
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Add files via upload
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2019-10-08 15:53:05 +08:00 |
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PKU-ZLR
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6218fa0ba4
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Add files via upload
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2019-10-08 01:32:09 +08:00 |
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PKU-ZLR
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bd8284e120
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Add files via upload
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2019-10-08 01:31:24 +08:00 |
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PKU-ZLR
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35574b0ee8
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Add files via upload
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2019-10-08 01:30:33 +08:00 |
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Feng Wang
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9471030908
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finish abc synthesis and the blif parser
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2019-09-26 14:59:48 +08:00 |
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王丰
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151ee5e89a
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initialization
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2019-09-26 14:00:28 +08:00 |