4556425d58
upgrade to latest RocketChip
...
* Scala updates to 2.11.12
* Bootrom code moved to testchipip
* Makefrag for testchipip blackboxes moved to testchipip
* Added support for block device
2018-04-18 17:49:15 -07:00
3ca6ba6f94
Add a top level zynq project and link against RC
2016-08-10 18:02:59 -07:00
cfc0a61f30
move AXI to HTIF conversion to Chisel-generated module
2016-02-19 13:53:12 -08:00
dc5bd0e0d1
move common tcl to vivado 2015.4
2016-01-06 09:34:47 -08:00
b3088fe4a1
zedboard project generation upgraded to vivado 2015.2
2015-07-14 18:26:54 -07:00
366d905909
better support for multiple CONFIGs
...
Now there will be a project per CONFIG. This also generates the associated tcl and verilog files for each CONFIG.
2015-06-30 12:46:52 -07:00
1ab1a2ecef
updates to handle vivado 2014.4
2015-01-07 16:17:56 -08:00
0cc12a9a95
support for using chisel configs and calling into rocket-chip to generate new verilog
2014-09-19 18:02:35 -07:00
b7a4a40ec9
redo 2014.2 upgrade
...
this re-applies 307119ea47027d75bd2f
2014-09-15 19:11:10 -07:00
9d66329c59
zybo manually replace PS xci/xml
2014-09-14 01:59:41 -07:00
027d75bd2f
Revert "upgrading common and zedboard to vivado 2014.2" until Zybo works
...
This reverts commit 307119ea47
2014-09-14 01:36:38 -07:00
307119ea47
upgrading common and zedboard to vivado 2014.2
2014-09-13 12:28:44 -07:00
913cc39c9a
separate common board name and official board name required by vivado
2014-09-12 21:44:36 -07:00
70879906fb
move fifos.v into wrapper.v
2014-09-11 16:29:58 -07:00
a4fa158677
can now build zedboard projects from tcl
2014-09-11 16:15:33 -07:00
d324f1163d
generic module name + tcl file
2014-09-10 23:02:27 -07:00
Howard Mao