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zedboard project generation upgraded to vivado 2015.2

This commit is contained in:
Scott Beamer 2015-07-14 18:26:54 -07:00
parent 366d905909
commit b3088fe4a1
2 changed files with 18 additions and 18 deletions
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16
common/zynq_rocketchip.tcl
View File

@ -1,10 +1,10 @@
#
# Vivado (TM) v2014.4 (64-bit)
# Vivado (TM) v2015.2 (64-bit)
#
# BOARD_NAME_HERE_rocketchip.tcl: Tcl script for re-creating project 'BOARD_NAME_HERE_rocketchip'
# BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE.tcl: Tcl script for re-creating project 'BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE'
#
# Generated by Vivado on Tue Jan 06 14:00:36 PST 2015
# IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
# Generated by Vivado on Tue Jul 14 17:36:16 PDT 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
@ -92,10 +92,10 @@ set_property "top" "rocketchip_wrapper" $obj
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part PART_NUMBER_HERE -flow {Vivado Synthesis 2014} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
create_run -name synth_1 -part PART_NUMBER_HERE -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2014" [get_runs synth_1]
set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property "needs_refresh" "1" $obj
@ -103,10 +103,10 @@ set_property "part" "PART_NUMBER_HERE" $obj
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part PART_NUMBER_HERE -flow {Vivado Implementation 2014} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
create_run -name impl_1 -part PART_NUMBER_HERE -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2014" [get_runs impl_1]
set_property flow "Vivado Implementation 2015" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property "needs_refresh" "1" $obj

20
zedboard/src/tcl/zedboard_bd.tcl
View File

@ -10,7 +10,7 @@
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2014.4
set scripts_vivado_version 2015.2
set current_vivado_version [version -short]
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
@ -32,6 +32,13 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
# create_project project_1 myproj -part xc7z020clg484-1
# set_property BOARD_PART em.avnet.com:zed:part0:1.0 [current_project]
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
# CHANGE DESIGN NAME HERE
set design_name system
@ -40,13 +47,6 @@ set design_name system
# you can create a design using the following command:
# create_bd_design $design_name
# CHECKING IF PROJECT EXISTS
if { [get_projects -quiet] eq "" } {
puts "ERROR: Please open or create a project!"
return 1
}
# Creating design if needed
set errMsg ""
set nRet 0
@ -149,7 +149,7 @@ proc create_root_design { parentCell } {
set M_AXI [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 M_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {25000000} CONFIG.PROTOCOL {AXI4} ] $M_AXI
set S_AXI [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI ]
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.DATA_WIDTH {64} CONFIG.FREQ_HZ {25000000} CONFIG.ID_WIDTH {6} CONFIG.MAX_BURST_LENGTH {16} CONFIG.NUM_READ_OUTSTANDING {1} CONFIG.NUM_WRITE_OUTSTANDING {1} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S_AXI
set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {64} CONFIG.FREQ_HZ {25000000} CONFIG.ID_WIDTH {6} CONFIG.MAX_BURST_LENGTH {16} CONFIG.NUM_READ_OUTSTANDING {1} CONFIG.NUM_WRITE_OUTSTANDING {1} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI4} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S_AXI
# Create ports
set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ]
@ -281,7 +281,7 @@ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} CONFIG.PCW_UIPARAM_DDR_TRAIN_
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {1} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} CONFIG.PCW_USE_S_AXI_HP0 {1} \
CONFIG.preset {ZedBoard*} ] $processing_system7_0
CONFIG.preset {ZedBoard} ] $processing_system7_0
# Create interface connections
connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_ports S_AXI] [get_bd_intf_pins axi_interconnect_1/S00_AXI]