f55bd8e9fc
purge icenet related C++ code
2018-07-07 17:37:34 -07:00
4556425d58
upgrade to latest RocketChip
...
* Scala updates to 2.11.12
* Bootrom code moved to testchipip
* Makefrag for testchipip blackboxes moved to testchipip
* Added support for block device
2018-04-18 17:49:15 -07:00
4400930abf
Linux boot documentation fix ( #44 )
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* Update README to reflect changes in BBL, remove unneeded make recipes
2017-03-17 14:16:17 -07:00
feb370de1c
Manage firrtl dependency manually
2017-03-09 17:47:58 -08:00
eb96e9db7f
replace init-rocket-submodule with init-submodules rule in Makefrag
2016-11-01 13:34:54 -07:00
3ed82263c4
use TestDriver.v in rocket-chip not in testchipip
2016-10-24 17:19:32 -07:00
33b1e90efc
make sure to use the correct kind of include for Makefrag.pkgs
2016-10-24 17:19:08 -07:00
31f0bd2422
make sure library stamps have correct dependencies
2016-10-11 11:42:46 -07:00
f6978c40e0
make submodule building more extensible
2016-10-10 16:42:09 -07:00
07c02e7a0f
SAI renamed to TSI
2016-10-07 15:20:38 -07:00
79697316de
replace dtm driver with sai driver
2016-10-05 09:26:49 -07:00
5cddc881ad
move SerialAdapter code to testchipip
2016-10-04 14:52:49 -07:00
75b4ea3775
add our own version of the bootrom
2016-10-04 13:23:50 -07:00
3f3e755d6a
fix up makefiles
2016-10-03 16:59:41 -07:00
bf036fb956
start implementing alternate adapter interface
2016-09-29 12:44:47 -07:00
6c06d97cb1
Conform to new rocketchip generator. Fix adapter concat bugs
...
This brings fpga-zynq up to sync with Henry's changes to rocket-chip
generation utilities. It also fixes a silly bug that assumed constant
field orderings when toBits-ing an aggregate.
2016-09-08 16:48:59 -07:00
74ed9ea984
Fix copy of generated verilog to project
2016-08-17 16:45:30 -07:00
33dcf3efa7
Makefile bug fixes, generator config lookup enhancement
2016-08-17 14:10:53 -07:00
9bfaca46a0
Update readme, enable config lookup from multiple projects
2016-08-12 16:39:18 -07:00
e4a8b949f4
Merge branch 'master' of github.com:ucb-bar/fpga-zynq into dtm_bring_up
2016-08-10 18:21:55 -07:00
3ca6ba6f94
Add a top level zynq project and link against RC
2016-08-10 18:02:59 -07:00
0b3237681b
Add DTM driver and new zynq main
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Test changes on other platforms + cleanup
2016-08-10 18:02:54 -07:00
5810ebf0f3
Use /bin/bash to support brace expansion
2016-02-26 00:00:26 -05:00
cfc0a61f30
move AXI to HTIF conversion to Chisel-generated module
2016-02-19 13:53:12 -08:00
9061bc3081
all boards should use rocketchip_wrapper.bit for symlink
2015-08-04 15:56:42 -07:00
366d905909
better support for multiple CONFIGs
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Now there will be a project per CONFIG. This also generates the associated tcl and verilog files for each CONFIG.
2015-06-30 12:46:52 -07:00
1ab1a2ecef
updates to handle vivado 2014.4
2015-01-07 16:17:56 -08:00
d2eb1e9a59
Fix CHISEL_CONFIG -> CONFIG in Makefrag
2014-10-03 16:44:09 -07:00
19243ebb15
renaming CHISEL_CONFIG to CONFIG
...
this way it can be easily overriden in the same way as rocket-chip
2014-10-01 13:48:06 -07:00
cacaf66639
use variable for s3 path
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we should also figure out https and general url
2014-09-25 22:55:42 -07:00
08667b420e
fix bug in for image copying
2014-09-25 22:48:58 -07:00
45f5a624fa
fetch ramdisk, build from output.bif, finish up readme content
2014-09-25 22:13:27 -07:00
d177f579b9
add fetch-riscv-linux targets
2014-09-25 17:39:49 -07:00
f64585c1de
fix makefrag bug and tidy up
2014-09-25 14:04:14 -07:00
53d7009dc0
tidying up main makefrag
2014-09-24 17:12:28 -07:00
612956b221
fix submodules in Makefrag
2014-09-24 07:53:05 -07:00
e7b0249cba
add dtb compilation target: make arm-dtb
2014-09-21 18:30:41 -07:00
f1071df249
add make targets for arm-linux and arm-uboot
2014-09-21 18:22:42 -07:00
0cc12a9a95
support for using chisel configs and calling into rocket-chip to generate new verilog
2014-09-19 18:02:35 -07:00
6d53e19baa
opening and closing ramdisk
2014-09-19 14:54:09 -07:00
00267721d3
make project default target
2014-09-19 10:37:50 -07:00
98625e850c
add target for vivado gui back to make
2014-09-18 18:11:52 -07:00
51b5717b80
bitfile -> bitstream
2014-09-18 18:09:29 -07:00
15dcd8dadf
improvements to makefile automation
2014-09-18 17:44:45 -07:00
5139b703e0
no longer use bd files for zybo since done by tcl
2014-09-15 20:06:52 -07:00
9d66329c59
zybo manually replace PS xci/xml
2014-09-14 01:59:41 -07:00
892d6f7b02
fix Makefrag support for boards with no model (zybo)
2014-09-13 12:22:39 -07:00
5524f27c2c
add zedboard board model and simplify replacement names
2014-09-13 11:19:58 -07:00
913cc39c9a
separate common board name and official board name required by vivado
2014-09-12 21:44:36 -07:00
d85d0953b8
fix tcl pathnames
2014-09-12 18:03:41 -07:00
Howard Mao