tidying up main makefrag
This commit is contained in:
Scott Beamer
parent
09a7ceaf25
commit
53d7009dc0
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@ -2,12 +2,14 @@
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JOBS = 16
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base_dir = $(abspath ..)
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common = $(base_dir)/common
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output_delivery = deliver_output
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ifneq ($(BOARD_MODEL),)
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insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board" "$(BOARD_MODEL)"/g
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insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board" "$(BOARD_MODEL)"/g
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endif
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verilog_srcs = \
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src/verilog/clocking.vh \
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src/verilog/rocketchip_wrapper.v \
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@ -19,41 +21,48 @@ default: project
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# Specialize sources for board
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src/verilog/rocketchip_wrapper.v: $(base_dir)/common/rocketchip_wrapper.v
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cp $(base_dir)/common/rocketchip_wrapper.v src/verilog/
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# ------------------------------------------------------------------------------
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src/verilog/rocketchip_wrapper.v: $(common)/rocketchip_wrapper.v
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cp $(common)/rocketchip_wrapper.v src/verilog/
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src/tcl/$(BOARD)_rocketchip.tcl: $(base_dir)/common/zynq_rocketchip.tcl Makefile
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sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/PART_NUMBER_HERE/$(PART)/g;$(insert_board);s/CHISEL_CONFIG_HERE/$(CHISEL_CONFIG)/g' $(base_dir)/common/zynq_rocketchip.tcl > src/tcl/$(BOARD)_rocketchip.tcl
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src/tcl/$(BOARD)_rocketchip.tcl: $(common)/zynq_rocketchip.tcl Makefile
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sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/PART_NUMBER_HERE/$(PART)/g;$(insert_board);s/CHISEL_CONFIG_HERE/$(CHISEL_CONFIG)/g' \
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$(common)/zynq_rocketchip.tcl > src/tcl/$(BOARD)_rocketchip.tcl
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src/tcl/make_bitstream.tcl: $(base_dir)/common/make_bitstream.tcl
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sed 's/BOARD_NAME_HERE/$(BOARD)/g' $(base_dir)/common/make_bitstream.tcl > src/tcl/make_bitstream.tcl
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src/tcl/make_bitstream.tcl: $(common)/make_bitstream.tcl
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sed 's/BOARD_NAME_HERE/$(BOARD)/g' \
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$(common)/make_bitstream.tcl > src/tcl/make_bitstream.tcl
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# no dependencies so it has to be manually called
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# (don't want to clobber local verilog by accident)
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rocket:
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cd $(base_dir)/rocket-chip/fsim; make verilog CONFIG=$(CHISEL_CONFIG); cp generated-src/Top.$(CHISEL_CONFIG).v $(base_dir)/$(BOARD)/src/verilog
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cd $(base_dir)/rocket-chip/fsim; \
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make verilog CONFIG=$(CHISEL_CONFIG); \
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cp generated-src/Top.$(CHISEL_CONFIG).v $(base_dir)/$(BOARD)/src/verilog
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# Project generation
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$(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr: src/verilog/rocketchip_wrapper.v src/tcl/$(BOARD)_rocketchip.tcl
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vivado -mode tcl -source src/tcl/$(BOARD)_rocketchip.tcl
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# ------------------------------------------------------------------------------
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project = $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr
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$(project): | src/verilog/rocketchip_wrapper.v src/tcl/$(BOARD)_rocketchip.tcl
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vivado -mode tcl -source src/tcl/$(BOARD)_rocketchip.tcl; \
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project: $(project)
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$(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr src/tcl/make_bitstream.tcl $(verilog_srcs) src/constrs/base.xdc
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vivado: $(project)
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vivado $(project) &
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bitstream = $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit
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$(bitstream): src/tcl/make_bitstream.tcl $(verilog_srcs) src/constrs/base.xdc | $(project)
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vivado -mode tcl -source src/tcl/make_bitstream.tcl
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bitstream: $(bitstream)
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project: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr
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vivado: $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr
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vivado $(BOARD)_rocketchip/$(BOARD)_rocketchip.xpr &
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bitstream: $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit
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# Platform software generation
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# ------------------------------------------------------------------------------
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arm_linux_dir = $(base_dir)/common/linux-xlnx
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uboot_dir = $(base_dir)/common/u-boot-xlnx
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soft_build_dir = soft_build
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# software builds
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arm-linux: arm-uboot # must first build uboot because we need tools
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# compile kernel
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git submodule update --init $(arm_linux_dir)
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@ -83,11 +92,15 @@ arm-uboot:
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arm-dtb:
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export PATH=$(arm_linux_dir)/scripts/dtc:$$PATH && dtc -I dts -O dtb -o $(output_delivery)/devicetree.dtb soft_config/$(BOARD)_devicetree.dts
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# Handle images and git submodule for prebuilt modules
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# ------------------------------------------------------------------------------
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# boot.bif is proxy for has images submodule been pulled
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fpga-images-$(BOARD)/boot.bif:
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git submodule update --init --depth=1 fpga-images-$(BOARD)
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fpga-images-$(BOARD)/boot.bin: fpga-images-$(BOARD)/boot.bif $(BOARD)_rocketchip/$(BOARD)_rocketchip.runs/impl_1/rocketchip_wrapper.bit
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fpga-images-$(BOARD)/boot.bin: fpga-images-$(BOARD)/boot.bif $(bitstream)
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cd fpga-images-$(BOARD); bootgen -image boot.bif -w -o boot.bin
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fetch-images: fpga-images-$(BOARD)/boot.bif
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@ -110,7 +123,8 @@ ramdisk-close:
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rm uramdisk.cpio.gz
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@echo "Don't forget to remove ramdisk before opening it again (sudo rm -rf ramdisk)"
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clean:
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rm -f *.log *.jou
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.PHONY: rocket project vivado bitstream fetch-images load-sd clean ramdisk-open ramdisk-close
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clean:
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rm -f *.log *.jou *.str
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.PHONY: rocket vivado fetch-images load-sd clean ramdisk-open ramdisk-close
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