2014-09-19 08:44:45 +08:00
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# This makefrag is sourced by each board's subdirectory
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2014-09-22 09:22:42 +08:00
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JOBS = 16
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2014-09-11 08:53:33 +08:00
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base_dir = $(abspath ..)
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2014-09-25 08:12:28 +08:00
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common = $(base_dir)/common
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2014-09-22 09:22:42 +08:00
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output_delivery = deliver_output
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2014-09-11 08:53:33 +08:00
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2014-09-14 03:22:39 +08:00
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ifneq ($(BOARD_MODEL),)
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2015-01-07 11:23:19 +08:00
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insert_board = s/\# REPLACE FOR OFFICIAL BOARD NAME/set_property "board_part" "$(BOARD_MODEL)"/g
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2014-09-14 03:22:39 +08:00
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endif
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2014-09-11 08:53:33 +08:00
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2015-07-01 03:46:35 +08:00
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proj_name = $(BOARD)_rocketchip_$(CONFIG)
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2014-09-25 08:12:28 +08:00
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2014-09-19 08:44:45 +08:00
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verilog_srcs = \
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src/verilog/clocking.vh \
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src/verilog/rocketchip_wrapper.v \
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2014-10-04 07:44:09 +08:00
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src/verilog/Top.$(CONFIG).v \
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2014-09-19 08:44:45 +08:00
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2014-09-11 08:53:33 +08:00
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2014-09-20 01:37:50 +08:00
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default: project
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2014-09-19 08:44:45 +08:00
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# Specialize sources for board
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2014-09-25 08:12:28 +08:00
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# ------------------------------------------------------------------------------
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src/verilog/rocketchip_wrapper.v: $(common)/rocketchip_wrapper.v
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cp $(common)/rocketchip_wrapper.v src/verilog/
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2014-09-11 08:53:33 +08:00
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2015-07-01 03:46:35 +08:00
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src/tcl/$(proj_name).tcl: $(common)/zynq_rocketchip.tcl Makefile
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2014-10-04 07:44:09 +08:00
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sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/PART_NUMBER_HERE/$(PART)/g;$(insert_board);s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \
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2015-07-01 03:46:35 +08:00
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$(common)/zynq_rocketchip.tcl > src/tcl/$(proj_name).tcl
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2014-09-11 14:37:47 +08:00
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2015-07-01 03:46:35 +08:00
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src/tcl/make_bitstream_$(CONFIG).tcl: $(common)/make_bitstream.tcl
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sed 's/BOARD_NAME_HERE/$(BOARD)/g;s/CHISEL_CONFIG_HERE/$(CONFIG)/g' \
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$(common)/make_bitstream.tcl > src/tcl/make_bitstream_$(CONFIG).tcl
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2014-09-19 08:44:45 +08:00
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2014-09-20 09:02:35 +08:00
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rocket:
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2014-09-25 08:12:28 +08:00
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cd $(base_dir)/rocket-chip/fsim; \
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2014-10-02 04:48:06 +08:00
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make verilog CONFIG=$(CONFIG); \
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cp generated-src/Top.$(CONFIG).v $(base_dir)/$(BOARD)/src/verilog
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2014-09-20 09:02:35 +08:00
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2014-09-19 08:44:45 +08:00
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2014-09-20 01:37:50 +08:00
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2014-09-19 08:44:45 +08:00
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# Project generation
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2014-09-25 08:12:28 +08:00
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# ------------------------------------------------------------------------------
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2015-07-01 03:46:35 +08:00
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project = $(proj_name)/$(proj_name).xpr
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$(project): | src/verilog/rocketchip_wrapper.v src/tcl/$(proj_name).tcl
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vivado -mode tcl -source src/tcl/$(proj_name).tcl;
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2014-09-25 08:12:28 +08:00
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project: $(project)
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2014-09-19 08:44:45 +08:00
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2014-09-25 08:12:28 +08:00
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vivado: $(project)
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vivado $(project) &
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2014-09-19 08:44:45 +08:00
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2015-07-01 03:46:35 +08:00
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bitstream = $(proj_name)/$(proj_name).runs/impl_1/rocketchip_wrapper.bit
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$(bitstream): src/tcl/make_bitstream_$(CONFIG).tcl $(verilog_srcs) src/constrs/base.xdc | $(project)
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vivado -mode tcl -source src/tcl/make_bitstream_$(CONFIG).tcl
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2014-09-25 08:12:28 +08:00
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bitstream: $(bitstream)
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2014-09-20 01:37:50 +08:00
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2014-09-25 08:12:28 +08:00
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# Platform software generation
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# ------------------------------------------------------------------------------
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2014-09-22 09:22:42 +08:00
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arm_linux_dir = $(base_dir)/common/linux-xlnx
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uboot_dir = $(base_dir)/common/u-boot-xlnx
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soft_build_dir = soft_build
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arm-linux: arm-uboot # must first build uboot because we need tools
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# compile kernel
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2014-09-24 22:53:05 +08:00
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git submodule update --init $(arm_linux_dir)
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2014-09-22 09:22:42 +08:00
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# no make clean included here since one copy of linux should work on all boards
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cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig
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cd $(arm_linux_dir) && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS)
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# convert zImage to uImage
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cd $(arm_linux_dir) && export PATH=$(uboot_dir)/tools:$$PATH && make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- UIMAGE_LOADADDR=0x8000 uImage
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mkdir -p $(output_delivery)
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cp $(arm_linux_dir)/arch/arm/boot/uImage $(output_delivery)/
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arm-uboot:
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# compile board-compatible u-boot
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2014-09-24 22:53:05 +08:00
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git submodule update --init $(uboot_dir)
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2014-09-22 09:22:42 +08:00
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# copy relevant configuration files
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if [ -a soft_config/boards.cfg ] ; \
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then \
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cp soft_config/boards.cfg $(uboot_dir)/ ; \
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fi;
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cp soft_config/zynq_$(UBOOT_CONFIG).h $(uboot_dir)/include/configs/
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# actually build
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cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- zynq_$(UBOOT_CONFIG)_config
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cd $(uboot_dir) && make CROSS_COMPILE=arm-xilinx-linux-gnueabi- -j$(JOBS)
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mkdir -p $(soft_build_dir)
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cp $(uboot_dir)/u-boot $(soft_build_dir)/u-boot.elf
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2014-09-19 08:44:45 +08:00
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2014-09-22 09:30:41 +08:00
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arm-dtb:
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export PATH=$(arm_linux_dir)/scripts/dtc:$$PATH && dtc -I dts -O dtb -o $(output_delivery)/devicetree.dtb soft_config/$(BOARD)_devicetree.dts
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2014-09-25 08:12:28 +08:00
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2014-09-20 05:54:09 +08:00
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# Handle images and git submodule for prebuilt modules
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2014-09-25 08:12:28 +08:00
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# ------------------------------------------------------------------------------
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2014-09-26 05:04:14 +08:00
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images = fpga-images-$(BOARD)/boot.bif
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$(images):
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2014-09-19 08:44:45 +08:00
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git submodule update --init --depth=1 fpga-images-$(BOARD)
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2014-09-26 05:04:14 +08:00
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fetch-images: $(images)
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2014-09-19 08:44:45 +08:00
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2014-09-26 05:04:14 +08:00
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fpga-images-$(BOARD)/boot.bin: $(images) $(bitstream)
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2015-07-01 03:46:35 +08:00
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ln -sf ../../$(bitstream) fpga-images-$(BOARD)/boot_image/system.bit
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2014-09-26 05:04:14 +08:00
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cd fpga-images-$(BOARD); bootgen -image boot.bif -w -o boot.bin
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2014-09-19 08:44:45 +08:00
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2014-09-26 13:48:58 +08:00
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load-sd: $(images)
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2014-09-19 08:44:45 +08:00
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$(base_dir)/common/load_card.sh $(SD)
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2014-09-12 07:15:15 +08:00
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2014-09-26 05:04:14 +08:00
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ramdisk-open: $(images)
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2014-09-20 05:54:09 +08:00
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mkdir ramdisk
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dd if=fpga-images-$(BOARD)/uramdisk.image.gz bs=64 skip=1 | \
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gunzip -c | sudo sh -c 'cd ramdisk/ && cpio -i'
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ramdisk-close:
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@if [ ! -d "ramdisk" ]; then \
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echo "No ramdisk to close (use make ramdisk-open first)"; \
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exit 1; \
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fi
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sh -c 'cd ramdisk/ && sudo find . | sudo cpio -H newc -o' | gzip -9 > uramdisk.cpio.gz
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mkimage -A arm -O linux -T ramdisk -d uramdisk.cpio.gz fpga-images-$(BOARD)/uramdisk.image.gz
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rm uramdisk.cpio.gz
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@echo "Don't forget to remove ramdisk before opening it again (sudo rm -rf ramdisk)"
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2014-09-20 01:37:50 +08:00
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2014-09-25 08:12:28 +08:00
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2014-09-26 13:13:27 +08:00
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# Fetch ramdisk for user building from scratch
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# ------------------------------------------------------------------------------
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2014-09-26 13:55:42 +08:00
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s3_url = https://s3-us-west-1.amazonaws.com/riscv.org/fpga-zynq-files
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ramdisk_url = $(s3_url)/uramdisk.image.gz
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2014-09-26 13:13:27 +08:00
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fetch-ramdisk:
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mkdir -p $(output_delivery)
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curl $(ramdisk_url) > $(output_delivery)/uramdisk.image.gz
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# Rebuild from bif for user building from scratch
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# ------------------------------------------------------------------------------
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$(output_delivery)/boot.bin:
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cd $(output_delivery); bootgen -image output.bif -w -o boot.bin
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2014-09-26 08:39:49 +08:00
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# Fetch pre-built risc-v linux binary and root fs from S3
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# ------------------------------------------------------------------------------
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2014-09-26 13:55:42 +08:00
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riscv_root_bin = $(s3_url)/root.bin
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2014-09-26 08:39:49 +08:00
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ifeq ($(BOARD), zybo)
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2014-09-26 13:55:42 +08:00
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riscv_vmlinux = $(s3_url)/vmlinux_nofpu
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2014-09-26 08:39:49 +08:00
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else
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2014-09-26 13:55:42 +08:00
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riscv_vmlinux = $(s3_url)/vmlinux
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2014-09-26 08:39:49 +08:00
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endif
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sd_riscv = fpga-images-$(BOARD)/riscv
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sd_riscv_scratch = $(output_delivery)/riscv
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fetch-riscv-linux:
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mkdir -p $(sd_riscv)
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curl $(riscv_root_bin) > $(sd_riscv)/root.bin
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curl $(riscv_vmlinux) > $(sd_riscv)/vmlinux
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fetch-riscv-linux-deliver:
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mkdir -p $(sd_riscv_scratch)
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curl $(riscv_root_bin) > $(sd_riscv_scratch)/root.bin
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curl $(riscv_vmlinux) > $(sd_riscv_scratch)/vmlinux
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2014-09-12 07:15:15 +08:00
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clean:
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2014-09-25 08:12:28 +08:00
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rm -f *.log *.jou *.str
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2014-09-20 01:37:50 +08:00
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2014-09-26 05:04:14 +08:00
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.PHONY: vivado rocket fetch-images load-sd ramdisk-open ramdisk-close clean
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