fpga-pynq/common/Makefrag

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base_dir = $(abspath ..)
.PHONY: all
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all: verilog tcl
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rtl/rocketchip_wrapper.v: $(base_dir)/common/rocketchip_wrapper.v
cp $(base_dir)/common/rocketchip_wrapper.v rtl/
rtl/fifos.v: $(base_dir)/common/fifos.v
cp $(base_dir)/common/fifos.v rtl/
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hw/zynq_rocketchip.tcl: $(base_dir)/common/zynq_rocketchip.tcl
sed 's/PART_NUMBER_HERE/$(PART)/' $(base_dir)/common/zynq_rocketchip.tcl > hw/zynq_rocketchip.tcl
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.PHONY: verilog
verilog: rtl/rocketchip_wrapper.v rtl/fifos.v
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.PHONY: tcl
tcl: hw/zynq_rocketchip.tcl