fpga-pynq/common/zynq_rocketchip.tcl

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#
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# Vivado (TM) v2015.4 (64-bit)
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#
# BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE.tcl: Tcl script for re-creating project 'BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE'
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#
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# Generated by Vivado on Tue Jan 05 14:52:20 PST 2016
# IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
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#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."
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# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
variable script_file
set script_file "BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE.tcl"
# Help information for this script
proc help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < [llength $::argc]} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE"]"
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# Create project
create_project BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE $orig_proj_dir
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# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [get_projects BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE]
set_property "default_lib" "xil_defaultlib" $obj
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set_property "part" "PART_NUMBER_HERE" $obj
# REPLACE FOR OFFICIAL BOARD NAME $obj
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set_property "simulator_language" "Mixed" $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
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create_fileset -srcset sources_1
}
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
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set files [list \
"[file normalize "$origin_dir/src/verilog/clocking.vh"]"\
"[file normalize "$origin_dir/src/verilog/Top.CHISEL_CONFIG_HERE.v"]"\
"[file normalize "$origin_dir/src/verilog/rocketchip_wrapper.v"]"\
"[file normalize "$origin_dir/src/verilog/AsyncResetReg.v"]" \
"[file normalize "$origin_dir/src/verilog/plusarg_reader.v"]" \
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]
add_files -norecurse -fileset $obj $files
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# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
# None
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property "top" "rocketchip_wrapper" $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
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create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
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set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/src/constrs/base.xdc"]"
set file_added [add_files -norecurse -fileset $obj $file]
set file "$origin_dir/src/constrs/base.xdc"
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set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
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set_property "file_type" "XDC" $file_obj
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property "target_constrs_file" "[file normalize "$origin_dir/src/constrs/base.xdc"]" $obj
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# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
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create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
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set obj [get_filesets sim_1]
# Empty (no sources present)
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property "top" "rocketchip_wrapper" $obj
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part PART_NUMBER_HERE -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
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} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
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}
set obj [get_runs synth_1]
set_property "needs_refresh" "1" $obj
set_property "part" "PART_NUMBER_HERE" $obj
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part PART_NUMBER_HERE -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
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} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2015" [get_runs impl_1]
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}
set obj [get_runs impl_1]
set_property "needs_refresh" "1" $obj
set_property "part" "PART_NUMBER_HERE" $obj
puts "INFO: Project created:BOARD_NAME_HERE_rocketchip_CHISEL_CONFIG_HERE"
puts "INFO: Recreating block diagram from src/tcl/BOARD_NAME_HERE_bd.tcl"
source src/tcl/BOARD_NAME_HERE_bd.tcl
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exit