PyHCL/pyhcl/passes
raybdzhou 5bd670056a fix: errors in sequential logic simulation 2022-06-27 14:45:53 +08:00
..
__init__.py feat: add high form checking pass. 2022-03-11 18:18:46 +08:00
_pass.py feat: add high form checking pass. 2022-03-11 18:18:46 +08:00
auto_inferring.py refactor: func verilog_serialize in low_ir 2022-06-11 19:17:56 +08:00
check_flows.py fix: some bugs 2022-04-24 16:27:09 +08:00
check_form.py refactor: low_ir.py 2022-05-04 22:45:58 +08:00
check_types.py refactor: func verilog_serialize in low_ir 2022-06-11 19:17:56 +08:00
check_widths.py fix: some bugs 2022-04-24 16:27:09 +08:00
expand_aggregate.py feat: add verilog_optimize 2022-06-10 17:49:38 +08:00
expand_memory.py feat: add expand_memory & optimize 2022-04-23 20:53:17 +08:00
expand_sequential.py refactor: func verilog_serialize in low_ir 2022-06-11 19:17:56 +08:00
expand_whens.py fix: bugs in expand_whens 2022-06-25 16:04:07 +08:00
handle_instance.py refactor: remove instance manager 2022-06-20 09:31:38 +08:00
optimize.py feat: Support for expanding nested static/dynamic access expressions 2022-04-29 23:33:22 +08:00
remove_access.py fix: bugs in replace_subaccess 2022-06-10 22:00:07 +08:00
replace_subaccess.py fix: errors in sequential logic simulation 2022-06-27 14:45:53 +08:00
utils.py fix: some bugs in replace_subaccess 2022-06-10 17:14:00 +08:00
verilog_optimize.py refactor: func verilog_serialize in low_ir 2022-06-11 19:17:56 +08:00
wir.py fix: replace type() with isinstance() in check passes. 2022-03-22 21:49:34 +08:00