forked from opendacs/PyHCL
81 lines
2.6 KiB
Python
81 lines
2.6 KiB
Python
from abc import ABC, abstractclassmethod
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from dataclasses import dataclass
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from pyhcl.ir import low_ir
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from pyhcl.passes.check_form import CheckHighForm
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from pyhcl.passes.check_types import CheckTypes
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from pyhcl.passes.check_flows import CheckFlow
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from pyhcl.passes.check_widths import CheckWidths
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from pyhcl.passes.auto_inferring import AutoInferring
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from pyhcl.passes.replace_subaccess import ReplaceSubaccess
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from pyhcl.passes.expand_aggregate import ExpandAggregate
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from pyhcl.passes.expand_whens import ExpandWhens
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from pyhcl.passes.expand_memory import ExpandMemory
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from pyhcl.passes.optimize import Optimize
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from pyhcl.passes.verilog_optimize import VerilogOptimize
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from pyhcl.passes.remove_access import RemoveAccess
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from pyhcl.passes.expand_sequential import ExpandSequential
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from pyhcl.passes.handle_instance import HandleInstance
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from pyhcl.passes.utils import AutoName
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class Form(ABC):
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@abstractclassmethod
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def emit(self) -> str:
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...
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@dataclass
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class HighForm(Form):
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c: low_ir.Circuit
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def emit(self) -> str:
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self.c = CheckHighForm(self.c).run()
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self.c = AutoInferring().run(self.c)
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self.c = CheckTypes().run(self.c)
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self.c = CheckFlow().run(self.c)
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self.c = CheckWidths().run(self.c)
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return self.c.serialize()
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@dataclass
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class MidForm(Form):
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def emit(self) -> str:
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...
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@dataclass
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class LowForm(Form):
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c: low_ir.Circuit
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def emit(self) -> str:
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AutoName()
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self.c = CheckHighForm(self.c).run()
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self.c = AutoInferring().run(self.c)
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self.c = CheckTypes().run(self.c)
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self.c = CheckFlow().run(self.c)
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self.c = CheckWidths().run(self.c)
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self.c = ExpandMemory().run(self.c)
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self.c = ReplaceSubaccess().run(self.c)
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self.c = ExpandAggregate().run(self.c)
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self.c = RemoveAccess().run(self.c)
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self.c = ExpandWhens().run(self.c)
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self.c = HandleInstance().run(self.c)
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self.c = Optimize().run(self.c)
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return self.c.serialize()
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@dataclass
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class Verilog(Form):
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c: low_ir.Circuit
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def emit(self) -> str:
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AutoName()
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self.c = CheckHighForm(self.c).run()
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self.c = AutoInferring().run(self.c)
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self.c = CheckTypes().run(self.c)
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self.c = CheckFlow().run(self.c)
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self.c = CheckWidths().run(self.c)
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self.c = ExpandAggregate().run(self.c)
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self.c = ReplaceSubaccess().run(self.c)
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self.c = RemoveAccess().run(self.c)
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self.c = VerilogOptimize().run(self.c)
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self.c = ExpandSequential().run(self.c)
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self.c = HandleInstance().run(self.c)
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self.c = Optimize().run(self.c)
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return self.c.verilog_serialize() |