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CommandGuide
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add heading for handshake-runner
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2021-01-12 21:59:28 +05:30 |
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Dialects
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Add documentation for Handshake dialect (#383)
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2021-01-05 01:33:39 +05:30 |
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ESI
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Rename all translate command line flags to use import and export
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2021-01-21 12:01:29 -08:00 |
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includes
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Add some more FIRRTL annotation documentation (#1330)
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2021-06-30 18:48:22 -07:00 |
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CMakeLists.txt
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[DOC] Add Doxygen documentation support (#362)
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2020-12-27 09:44:58 +05:30 |
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Charter.md
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Update reference to Calyx/Futil in the charter (#704)
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2021-03-02 10:02:27 -08:00 |
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FIRRTLAnnotations.md
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[FIRRTL][EmitMetadata] Add SitestBlackBox metadata support
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2021-09-24 12:53:09 -07:00 |
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GettingStarted.md
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[LLVM] Ditch LLVM mirror (#1761)
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2021-09-10 14:23:28 -07:00 |
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Passes.md
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Partially revert #1688 in favor of style used in upstream MLIR (#1698)
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2021-09-02 12:32:07 +01:00 |
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PythonBindings.md
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[Python] Re-work Python bindings using upstream improvements. (#1484)
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2021-07-29 09:49:58 -06:00 |
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RationaleComb.md
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[HW] Rename isCombinatorial -> isCombinational. NFC.
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2021-09-26 17:58:53 -07:00 |
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RationaleFIRRTL.md
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[FIRRTL][CHIRRTL] Add `memoryport.access` operations (#1539)
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2021-08-17 23:06:27 -07:00 |
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RationaleFSM.md
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[FSM] Update format of the rationale doc. NFC.
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2021-09-02 00:11:36 -05:00 |
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RationaleHW.md
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[HW Parameters] add the hw.param.value op.
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2021-09-26 17:55:01 -07:00 |
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RationaleSV.md
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[docs] more doc improvements.
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2021-09-25 14:15:10 -07:00 |
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RationaleSeq.md
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[Seq] Computational register op and lowering to SV (#883)
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2021-04-05 17:24:06 -07:00 |
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VerilogGeneration.md
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[ExportVerilog] Flip the default output of `sv.alwaysComb` ops (#1709)
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2021-09-06 22:44:16 -07:00 |
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dialects.drawio
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[RTL->HW] Rename the string "RTL" to "HW"
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2021-05-15 12:44:05 -07:00 |
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doxygen-mainpage.dox
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[DOC] Add Doxygen documentation support (#362)
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2020-12-27 09:44:58 +05:30 |
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doxygen.cfg.in
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[DOC] Add Doxygen documentation support (#362)
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2020-12-27 09:44:58 +05:30 |
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