[HW] Rename isCombinatorial -> isCombinational. NFC.

We agreed awhile ago that this was the right name.

docs/RationaleComb.md

@@ -35,7 +35,7 @@ TODO: Simple integer types, eventually parametricly wide integer type
 
 ### Zero-bit integer width is not supported
 
-Combinatorial operations like add and multiply work on values of signless
+Combinational operations like add and multiply work on values of signless
 standard integer types, e.g. `i42`, but they do not allow zero bit inputs.  This
 design point is motivated by a couple of reasons:
 

include/circt/Dialect/Comb/CombVisitors.h

@@ -19,7 +19,7 @@
 namespace circt {
 namespace comb {
 
-/// This helps visit Combinatorial nodes.
+/// This helps visit Combinational nodes.
 template <typename ConcreteType, typename ResultType = void,
           typename... ExtraArgs>
 class CombinationalVisitor {
@@ -52,7 +52,7 @@ public:
     abort();
   }
 
-  /// This callback is invoked on any combinatorial operations that are not
+  /// This callback is invoked on any combinational operations that are not
   /// handled by the concrete visitor.
   ResultType visitUnhandledComb(Operation *op, ExtraArgs... args) {
     return ResultType();

include/circt/Dialect/HW/HWOps.h

@@ -108,8 +108,8 @@ static inline StringRef getModuleResultName(Operation *module,
 void setModuleArgumentNames(Operation *module, ArrayRef<Attribute> names);
 void setModuleResultNames(Operation *module, ArrayRef<Attribute> names);
 
-/// Return true if the specified operation is a combinatorial logic op.
-bool isCombinatorial(Operation *op);
+/// Return true if the specified operation is a combinational logic op.
+bool isCombinational(Operation *op);
 
 /// Check parameter specified by `value` to see if it is valid within the scope
 /// of the specified module `module`.  If not, emit an error at the location of

include/circt/Dialect/HW/HWVisitors.h

@@ -43,11 +43,11 @@ public:
 
   /// This callback is invoked on any non-expression operations.
   ResultType visitInvalidTypeOp(Operation *op, ExtraArgs... args) {
-    op->emitOpError("unknown HW combinatorial node");
+    op->emitOpError("unknown HW combinational node");
     abort();
   }
 
-  /// This callback is invoked on any combinatorial operations that are not
+  /// This callback is invoked on any combinational operations that are not
   /// handled by the concrete visitor.
   ResultType visitUnhandledTypeOp(Operation *op, ExtraArgs... args) {
     return ResultType();
@@ -90,11 +90,11 @@ public:
 
   /// This callback is invoked on any non-expression operations.
   ResultType visitInvalidStmt(Operation *op, ExtraArgs... args) {
-    op->emitOpError("unknown HW combinatorial node");
+    op->emitOpError("unknown hw statement");
     abort();
   }
 
-  /// This callback is invoked on any combinatorial operations that are not
+  /// This callback is invoked on any combinational operations that are not
   /// handled by the concrete visitor.
   ResultType visitUnhandledTypeOp(Operation *op, ExtraArgs... args) {
     return ResultType();

lib/Dialect/HW/HWOps.cpp

@@ -21,8 +21,8 @@
 using namespace circt;
 using namespace hw;
 
-/// Return true if the specified operation is a combinatorial logic op.
-bool hw::isCombinatorial(Operation *op) {
+/// Return true if the specified operation is a combinational logic op.
+bool hw::isCombinational(Operation *op) {
   struct IsCombClassifier : public TypeOpVisitor<IsCombClassifier, bool> {
     bool visitInvalidTypeOp(Operation *op) { return false; }
     bool visitUnhandledTypeOp(Operation *op) { return true; }

lib/Dialect/LLHD/Transforms/ProcessLoweringPass.cpp

@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Implement Pass to transform combinatorial processes to entities.
+// Implement Pass to transform combinational processes to entities.
 //
 //===----------------------------------------------------------------------===//
 

lib/Dialect/SV/Transforms/PrettifyVerilog.cpp

@@ -270,7 +270,7 @@ void PrettifyVerilogPass::processPostOrder(Block &body) {
     // expression inline in the best case, and better scopes the temporary wire
     // they generate in the worst case.  Our overall traversal order is
     // post-order here which means all users will already be sunk.
-    if (hw::isCombinatorial(&op) || sv::isExpression(&op)) {
+    if (hw::isCombinational(&op) || sv::isExpression(&op)) {
       sinkExpression(&op);
       continue;
     }

lib/Translation/ExportVerilog/ExportVerilog.cpp

@@ -215,9 +215,9 @@ bool ExportVerilog::isVerilogExpression(Operation *op) {
   if (isa<ReadInOutOp, ArrayIndexInOutOp, ParamValueOp>(op))
     return true;
 
-  // All HW combinatorial logic ops and SV expression ops are Verilog
+  // All HW combinational logic ops and SV expression ops are Verilog
   // expressions.
-  return isCombinatorial(op) || isExpression(op);
+  return isCombinational(op) || isExpression(op);
 }
 
 /// Return the width of the specified type in bits or -1 if it isn't