circt/test
mikeurbach fba1ab7bfd
[AffineToStaticLogic] Flesh out support for converting to pipelines. (#2387)
This adds the necessary support to lower single affine loops to
pipelines. Broadly, this encompasses lowering affine structures like
if conditions into arithmetic, and building pipeline stages for each
scheduled group.
2021-12-24 10:30:55 -07:00
..
Analysis [SchedulingAnalysis] Support scf::IfOp and memref::LoadOp/StoreOp. (#2386) 2021-12-24 10:23:22 -07:00
CAPI [llvm] Update submodule to latest (#1589) 2021-08-18 19:37:43 -07:00
Conversion [AffineToStaticLogic] Flesh out support for converting to pipelines. (#2387) 2021-12-24 10:30:55 -07:00
Dialect [MSFT] Design partition support, part 3 (#2376) 2021-12-22 15:11:32 -08:00
Scheduling [Scheduling] Define problem to model operator chaining. (#2233) 2021-12-20 21:25:59 +01:00
Transforms [Transforms] Add --flatten-memref-calls pass (#2257) 2021-12-02 10:49:07 +00:00
circt-opt Add new CHIRRTL dialect 2021-12-08 18:02:15 -08:00
circt-reduce [reduce] Add `ConnectSourceOperandForwarder` reduction (#2369) 2021-12-20 22:06:07 +09:00
circt-translate [LLHD] remove the LLHD-specific Verilog printer. 2021-12-08 14:01:45 -08:00
firtool make firtool output options and pipeline structure a bit more sensible (#2358) 2021-12-17 10:14:43 -06:00
handshake-runner [Handshake] Move buffer insertion to Handshake transforms (#2381) 2021-12-23 08:33:51 +01:00
lib Partially revert #1688 in favor of style used in upstream MLIR (#1698) 2021-09-02 12:32:07 +01:00
verilator [Verilator] Make the error check more flexible (#264) 2020-11-20 11:37:13 -08:00
CMakeLists.txt Partially revert #1688 in favor of style used in upstream MLIR (#1698) 2021-09-02 12:32:07 +01:00
lit.cfg.py [reduce] Add a first proof-of-concept reducer implementation with sample FIRRTL dialect reducers (#1591) 2021-08-18 17:22:43 +02:00
lit.site.cfg.py.in Disable llhd-sim tests when the executable is not built (#1425) 2021-07-14 18:42:45 -04:00