Andrew Lenharth 8aec12cb90 [FIRRTL] use a trait to enforce FModuleOp's parent [NFC]		2021-04-21 09:31:25 -05:00
..
CAPI	[CAPI] Add CAPI for RTL InOutType getters and isa. (#845)	2021-03-30 10:26:02 -06:00
Conversion	[FIRRTL] Make names non-optional and use names as SSA values	2021-04-20 01:26:51 -07:00
Dialect	[FIRRTL] use a trait to enforce FModuleOp's parent [NFC]	2021-04-21 09:31:25 -05:00
ExportVerilog	[firtool] Change command line options for enabling passes	2021-04-14 13:27:25 -07:00
circt-opt	[Seq] Computational register op and lowering to SV (#883)	2021-04-05 17:24:06 -07:00
circt-translate	[firtool] Change command line options for enabling passes	2021-04-14 13:27:25 -07:00
firtool	Old build caused new build to pass. oops.	2021-04-16 15:13:12 -05:00
handshake-runner	Update LLVM (#792)	2021-03-19 11:33:33 -07:00
verilator	[Verilator] Make the error check more flexible (#264)	2020-11-20 11:37:13 -08:00
CMakeLists.txt	[ESI] Wrap modules exposing latency insensitive signals to expose ESI channels (#828)	2021-03-27 14:06:19 -07:00
lit.cfg.py	[ESI] Wrap modules exposing latency insensitive signals to expose ESI channels (#828)	2021-03-27 14:06:19 -07:00
lit.site.cfg.py.in	[LLHD] Add option to specify shared libs to load in llhd-sim (#789)	2021-03-19 08:10:36 -06:00