mirror of https://github.com/llvm/circt.git
61 lines
2.8 KiB
MLIR
61 lines
2.8 KiB
MLIR
// RUN: circt-translate --export-calyx --split-input-file --verify-diagnostics %s | FileCheck %s --strict-whitespace
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module attributes {calyx.entrypoint = "A"} {
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// CHECK-LABEL: extern "test.v" {
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// CHECK: primitive prim(in: 32) -> (out: 32);
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// CHECK: }
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hw.module.extern @prim(%in: i32) -> (out: i32) attributes {filename = "test.v"}
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// CHECK-LABEL: extern "test.v" {
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// CHECK: primitive params[WIDTH](in: WIDTH) -> (out: WIDTH);
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// CHECK: }
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hw.module.extern @params<WIDTH: i32>(%in: !hw.int<#hw.param.decl.ref<"WIDTH">>) -> (out: !hw.int<#hw.param.decl.ref<"WIDTH">>) attributes {filename = "test.v"}
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// CHECK-LABEL: component A<"static"=1>(in_0: 32, in_1: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (out_0: 32, out_1: 32, @done done: 1) {
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calyx.component @A(%in_0: i32, %in_1: i32, %go: i1 {go}, %clk: i1 {clk}, %reset: i1 {reset}) -> (%out_0: i32, %out_1: i32, %done: i1 {done}) {
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%c1_1 = hw.constant 1 : i1
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// CHECK: params_0 = params(32);
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%params.in, %params.out = calyx.primitive @params_0 of @params<WIDTH: i32 = 32> : i32, i32
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// CHECK: prim_0 = prim();
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%prim.in, %prim.out = calyx.primitive @prim_0 of @prim : i32, i32
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calyx.wires {
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// CHECK: done = 1'd1;
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calyx.assign %done = %c1_1 : i1
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// CHECK: params_0.in = in_0;
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calyx.assign %params.in = %in_0 : i32
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// CHECK: out_0 = params_0.out;
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calyx.assign %out_0 = %params.out : i32
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// CHECK: prim_0.in = in_1;
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calyx.assign %prim.in = %in_1 : i32
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// CHECK: out_1 = prim_0.out;
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calyx.assign %out_1 = %prim.out : i32
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}
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calyx.control {}
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} {static = 1}
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}
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// -----
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module attributes {calyx.entrypoint = "A"} {
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// CHECK-LABEL: extern "test.v" {
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// CHECK: primitive params[WIDTH](in: WIDTH, @clk clk: 1, @go go: 1) -> (out: WIDTH, @done done: 1);
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// CHECK: }
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hw.module.extern @params<WIDTH: i32>(%in: !hw.int<#hw.param.decl.ref<"WIDTH">>, %clk: i1 {calyx.clk}, %go: i1 {calyx.go}) -> (out: !hw.int<#hw.param.decl.ref<"WIDTH">>, done: i1 {calyx.done}) attributes {filename = "test.v"}
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// CHECK-LABEL: component A<"static"=1>(in_0: 32, in_1: 32, @go go: 1, @clk clk: 1, @reset reset: 1) -> (out_0: 32, out_1: 32, @done done: 1) {
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calyx.component @A(%in_0: i32, %in_1: i32, %go: i1 {go}, %clk: i1 {clk}, %reset: i1 {reset}) -> (%out_0: i32, %out_1: i32, %done: i1 {done}) {
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%c1_1 = hw.constant 1 : i1
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// CHECK: params_0 = params(32);
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%params.in, %params.clk, %params.go, %params.out, %params.done = calyx.primitive @params_0 of @params<WIDTH: i32 = 32> : i32, i1, i1, i32, i1
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calyx.wires {
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// CHECK: done = 1'd1;
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calyx.assign %done = %c1_1 : i1
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// CHECK: params_0.in = in_0;
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calyx.assign %params.in = %in_0 : i32
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// CHECK: out_0 = params_0.out;
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calyx.assign %out_0 = %params.out : i32
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}
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calyx.control {}
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} {static = 1}
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}
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