mirror of https://github.com/llvm/circt.git
7c11a9fa01
The `InferRW` pass transforms a memory with read and write ports to a single ReadWrite port memory, if it can prove that the read and write enable are mutually exclusive. The algorithm checks if any of the terms in the `And` expression tree of read and write enable is a complement of each other, to infer if the read and write enable are trivially mutually exclusive. The `RWmode` of the ReadWrite memory is set to `1` to use the memory in write mode and `0` for read mode. This PR sets the `RWmode` to the term in the `And` expression tree of the write enable, which proves the mutual exclusion, instead of setting it to the write enable. This is done to ensure equivalence with the `firrtl` compiler. For example, if, `write enable = A && B`, `read enable = C && ~B` implies `RWmode = B`. |
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