mirror of https://github.com/llvm/circt.git
108 lines
3.0 KiB
C++
108 lines
3.0 KiB
C++
//===- driver.cpp - Verilator software driver -----------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// A fairly standard, boilerplate Verilator C++ simulation driver. Assumes the
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// top level exposes just two signals: 'clk' and 'rst'.
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//
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//===----------------------------------------------------------------------===//
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#include "Vtop.h"
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#include "verilated_vcd_c.h"
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#include "signal.h"
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#include <iostream>
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vluint64_t timeStamp;
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// Stop the simulation gracefully on ctrl-c.
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volatile bool stopSimulation = false;
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void handle_sigint(int) { stopSimulation = true; }
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// Called by $time in Verilog.
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double sc_time_stamp() { return timeStamp; }
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int main(int argc, char **argv) {
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// Register graceful exit handler.
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signal(SIGINT, handle_sigint);
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Verilated::commandArgs(argc, argv);
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size_t numCyclesToRun = 0;
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bool runForever = true;
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// Search the command line args for those we are sensitive to.
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for (int i = 1; i < argc; ++i) {
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if (std::string(argv[i]) == "--cycles") {
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if (i + 1 < argc) {
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numCyclesToRun = std::strtoull(argv[++i], nullptr, 10);
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runForever = false;
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} else {
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std::cerr << "--cycles must be followed by number of cycles."
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<< std::endl;
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return 1;
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}
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}
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}
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// Construct the simulated module's C++ model.
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auto &dut = *new Vtop();
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char *waveformFile = getenv("SAVE_WAVE");
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VerilatedVcdC *tfp = nullptr;
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if (waveformFile) {
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#ifdef TRACE
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tfp = new VerilatedVcdC();
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Verilated::traceEverOn(true);
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dut.trace(tfp, 99); // Trace 99 levels of hierarchy
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tfp->open(waveformFile);
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std::cout << "[driver] Writing trace to " << waveformFile << std::endl;
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#else
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std::cout
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<< "[driver] Warning: waveform file specified, but not a debug build"
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<< std::endl;
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#endif
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}
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std::cout << "[driver] Starting simulation" << std::endl;
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// Reset.
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dut.rst = 1;
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dut.clk = 0;
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// Run for a few cycles with reset held.
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for (timeStamp = 0; timeStamp < 8 && !Verilated::gotFinish(); timeStamp++) {
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dut.eval();
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dut.clk = !dut.clk;
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if (tfp)
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tfp->dump(timeStamp);
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}
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// Take simulation out of reset.
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dut.rst = 0;
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// Run for the specified number of cycles out of reset.
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vluint64_t endTime = timeStamp + (numCyclesToRun * 2);
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for (; (runForever || timeStamp <= endTime) && !Verilated::gotFinish() &&
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!stopSimulation;
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timeStamp++) {
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dut.eval();
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dut.clk = !dut.clk;
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if (tfp)
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tfp->dump(timeStamp);
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}
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// Tell the simulator that we're going to exit. This flushes the output(s) and
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// frees whatever memory may have been allocated.
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dut.final();
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if (tfp)
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tfp->close();
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std::cout << "[driver] Ending simulation at tick #" << timeStamp << std::endl;
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return 0;
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}
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