mirror of https://github.com/llvm/circt.git
47 lines
2.4 KiB
MLIR
47 lines
2.4 KiB
MLIR
// RUN: circt-opt --verif-lower-symbolic-values=mode=extmodule %s | FileCheck --check-prefixes=CHECK,CHECK-EXTMODULE %s
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// RUN: circt-opt --verif-lower-symbolic-values=mode=yosys %s | FileCheck --check-prefixes=CHECK,CHECK-YOSYS %s
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// CHECK-LABEL: hw.module @Foo
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hw.module @Foo() {
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// CHECK-EXTMODULE-NOT: verif.symbolic_value
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// CHECK-YOSYS-NOT: verif.symbolic_value
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// CHECK-EXTMODULE: [[SYM:%.+]] = hw.instance {{.*}} @circt.symbolic_value.42<WIDTH: i32 = 42>
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// CHECK-YOSYS: [[TMP:%.+]] = sv.wire {sv.attributes = [#sv.attribute<"anyseq">]} : !hw.inout<i42>
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// CHECK-YOSYS: [[SYM:%.+]] = sv.read_inout [[TMP]]
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// CHECK: dbg.variable "x0", [[SYM]] : i42
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%0 = verif.symbolic_value : i42
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dbg.variable "x0", %0 : i42
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// CHECK-EXTMODULE: [[TMP:%.+]] = hw.instance {{.*}} @circt.symbolic_value.12<WIDTH: i32 = 12>
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// CHECK-EXTMODULE: [[SYM:%.+]] = hw.bitcast [[TMP]] : (i12) -> !hw.array<4xi3>
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// CHECK-YOSYS: [[TMP:%.+]] = sv.wire {sv.attributes = [#sv.attribute<"anyseq">]} : !hw.inout<array<4xi3>>
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// CHECK-YOSYS: [[SYM:%.+]] = sv.read_inout [[TMP]]
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// CHECK: dbg.variable "x1", [[SYM]] : !hw.array<4xi3>
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%1 = verif.symbolic_value : !hw.array<4xi3>
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dbg.variable "x1", %1 : !hw.array<4xi3>
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// Reuse existing extmodule for same i42 type.
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// CHECK-EXTMODULE: [[SYM:%.+]] = hw.instance {{.*}} @circt.symbolic_value.42<WIDTH: i32 = 42>
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// CHECK-YOSYS: [[TMP:%.+]] = sv.wire {sv.attributes = [#sv.attribute<"anyseq">]} : !hw.inout<i42>
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// CHECK-YOSYS: [[SYM:%.+]] = sv.read_inout [[TMP]]
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// CHECK: dbg.variable "x2", [[SYM]] : i42
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%2 = verif.symbolic_value : i42
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dbg.variable "x2", %2 : i42
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// Reuse existing extmodule for same 42 bit types, cast to array<6 x i7>.
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// CHECK-EXTMODULE: [[TMP:%.+]] = hw.instance {{.*}} @circt.symbolic_value.42<WIDTH: i32 = 42>
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// CHECK-EXTMODULE: [[SYM:%.+]] = hw.bitcast [[TMP]] : (i42) -> !hw.array<6xi7>
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// CHECK-YOSYS: [[TMP:%.+]] = sv.wire {sv.attributes = [#sv.attribute<"anyseq">]} : !hw.inout<array<6xi7>>
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// CHECK-YOSYS: [[SYM:%.+]] = sv.read_inout [[TMP]]
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// CHECK: dbg.variable "x3", [[SYM]] : !hw.array<6xi7>
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%3 = verif.symbolic_value : !hw.array<6xi7>
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dbg.variable "x3", %3 : !hw.array<6xi7>
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}
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// CHECK-EXTMODULE: hw.module.extern @circt.symbolic_value.42<WIDTH: i32>
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// CHECK-EXTMODULE-SAME: verilogName = "circt_symbolic_value"
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// CHECK-EXTMODULE: hw.module.extern @circt.symbolic_value.12<WIDTH: i32>
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// CHECK-EXTMODULE-SAME: verilogName = "circt_symbolic_value"
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