mirror of https://github.com/llvm/circt.git
59 lines
2.3 KiB
MLIR
59 lines
2.3 KiB
MLIR
// RUN: circt-opt --canonicalize %s | FileCheck %s
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// CHECK-LABEL: @HasBeenReset
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hw.module @HasBeenReset(in %clock: i1, in %reset: i1) {
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// CHECK-NEXT: %false = hw.constant false
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// CHECK-NEXT: %true = hw.constant true
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%false = hw.constant false
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%true = hw.constant true
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// CHECK-NEXT: %constResetA0 = hw.wire %false
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// CHECK-NEXT: %constResetA1 = hw.wire %false
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// CHECK-NEXT: %constResetS0 = hw.wire %false
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// CHECK-NEXT: %constResetS1 = hw.wire %false
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%r0 = verif.has_been_reset %clock, async %false
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%r1 = verif.has_been_reset %clock, async %true
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%r2 = verif.has_been_reset %clock, sync %false
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%r3 = verif.has_been_reset %clock, sync %true
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%constResetA0 = hw.wire %r0 sym @constResetA0 : i1
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%constResetA1 = hw.wire %r1 sym @constResetA1 : i1
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%constResetS0 = hw.wire %r2 sym @constResetS0 : i1
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%constResetS1 = hw.wire %r3 sym @constResetS1 : i1
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// CHECK-NEXT: [[TMP1:%.+]] = verif.has_been_reset %false, async %reset
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// CHECK-NEXT: [[TMP2:%.+]] = verif.has_been_reset %true, async %reset
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// CHECK-NEXT: %constClockA0 = hw.wire [[TMP1]]
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// CHECK-NEXT: %constClockA1 = hw.wire [[TMP2]]
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// CHECK-NEXT: %constClockS0 = hw.wire %false
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// CHECK-NEXT: %constClockS1 = hw.wire %false
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%c0 = verif.has_been_reset %false, async %reset
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%c1 = verif.has_been_reset %true, async %reset
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%c2 = verif.has_been_reset %false, sync %reset
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%c3 = verif.has_been_reset %true, sync %reset
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%constClockA0 = hw.wire %c0 sym @constClockA0 : i1
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%constClockA1 = hw.wire %c1 sym @constClockA1 : i1
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%constClockS0 = hw.wire %c2 sym @constClockS0 : i1
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%constClockS1 = hw.wire %c3 sym @constClockS1 : i1
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}
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// CHECK-LABEL: @clockedAssert
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hw.module @clockedAssert(in %clock : i1, in %a : i1, in %en : i1) {
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// CHECK: verif.clocked_assert %a if %en, posedge %clock : i1
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%clk = ltl.clock %a, posedge %clock : i1
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verif.assert %clk if %en : !ltl.sequence
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}
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// CHECK-LABEL: @clockedAssume
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hw.module @clockedAssume(in %clock : i1, in %a : i1, in %en : i1) {
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// CHECK: verif.clocked_assume %a if %en, posedge %clock : i1
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%clk = ltl.clock %a, posedge %clock : i1
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verif.assume %clk if %en : !ltl.sequence
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}
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// CHECK-LABEL: @clockedCover
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hw.module @clockedCover(in %clock : i1, in %a : i1, in %en : i1) {
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// CHECK: verif.clocked_cover %a if %en, posedge %clock : i1
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%clk = ltl.clock %a, posedge %clock : i1
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verif.cover %clk if %en : !ltl.sequence
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}
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