mirror of https://github.com/llvm/circt.git
219 lines
7.9 KiB
MLIR
219 lines
7.9 KiB
MLIR
// RUN: circt-opt --sim-proceduralize --canonicalize %s | FileCheck %s
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// CHECK-LABEL: @basic_print1
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// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
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// CHECK-NEXT: hw.triggered posedge %[[TRG]] {
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// CHECK-NEXT: %[[LIT:.*]] = sim.fmt.lit "Test"
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// CHECK-NEXT: sim.proc.print %[[LIT]]
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// CHECK-NEXT: }
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hw.module @basic_print1(in %clk : !seq.clock) {
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%true = hw.constant true
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%test = sim.fmt.lit "Test"
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sim.print %test on %clk if %true
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}
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// CHECK-LABEL: @basic_print2
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// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
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// CHECK-NEXT: hw.triggered posedge %[[TRG]](%cond) : i1 {
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// CHECK-NEXT: ^bb0(%[[ARG:.*]]: i1):
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// CHECK-DAG: %[[LIT1:.*]] = sim.fmt.lit "Not with a bang but a \00"
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// CHECK-DAG: %[[LIT0:.*]] = sim.fmt.lit "This is the way the world ends\0A"
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// CHECK: scf.if %[[ARG]] {
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// CHECK-NEXT: sim.proc.print %[[LIT0]]
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// CHECK-NEXT: sim.proc.print %[[LIT0]]
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// CHECK-NEXT: sim.proc.print %[[LIT0]]
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// CHECK-NEXT: sim.proc.print %[[LIT1]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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hw.module @basic_print2(in %clk : !seq.clock, in %cond : i1) {
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%0 = sim.fmt.lit "Not with a bang but a \00"
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%1 = sim.fmt.lit "This is the way the world ends\0A"
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sim.print %1 on %clk if %cond
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sim.print %1 on %clk if %cond
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sim.print %1 on %clk if %cond
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sim.print %0 on %clk if %cond
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}
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// CHECK-LABEL: @basic_print3
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// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
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// CHECK-NEXT: hw.triggered posedge %[[TRG]](%val) : i32 {
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// CHECK-NEXT: ^bb0(%[[ARG:.*]]: i32):
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// CHECK-DAG: %[[LB:.*]] = sim.fmt.lit "Bin: "
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// CHECK-DAG: %[[LD:.*]] = sim.fmt.lit ", Dec: "
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// CHECK-DAG: %[[LH:.*]] = sim.fmt.lit ", Hex: "
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// CHECK-DAG: %[[FB:.*]] = sim.fmt.bin %[[ARG]] : i32
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// CHECK-DAG: %[[FD:.*]] = sim.fmt.dec %[[ARG]] : i32
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// CHECK-DAG: %[[FH:.*]] = sim.fmt.hex %[[ARG]] : i32
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// CHECK-DAG: %[[CAT:.*]] = sim.fmt.concat (%[[LB]], %[[FB]], %[[LD]], %[[FD]], %[[LH]], %[[FH]])
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// CHECK: sim.proc.print %[[CAT]]
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// CHECK-NEXT: }
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hw.module @basic_print3(in %clk : !seq.clock, in %val: i32) {
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%true = hw.constant true
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%comma = sim.fmt.lit ", "
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%bin_lit = sim.fmt.lit "Bin: "
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%bin_val = sim.fmt.bin %val : i32
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%bin_cat = sim.fmt.concat (%bin_lit, %bin_val)
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%dec_lit = sim.fmt.lit "Dec: "
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%dec_val = sim.fmt.dec %val : i32
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%dec_cat = sim.fmt.concat (%dec_lit, %dec_val)
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%hex_lit = sim.fmt.lit "Hex: "
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%hex_val = sim.fmt.hex %val : i32
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%hex_cat = sim.fmt.concat (%hex_lit, %hex_val)
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%str = sim.fmt.concat (%bin_cat, %comma, %dec_cat, %comma, %hex_cat)
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sim.print %str on %clk if %true
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}
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// CHECK-LABEL: @multi_args
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// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
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// CHECK-NEXT: hw.triggered posedge %0(%a, %b, %c) : i8, i8, i8 {
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// CHECK-NEXT: ^bb0(%[[ARG0:.*]]: i8, %[[ARG1:.*]]: i8, %[[ARG2:.*]]: i8):
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// CHECK-DAG: %[[COM:.*]] = sim.fmt.lit ", "
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// CHECK-DAG: %[[B0:.*]] = sim.fmt.bin %[[ARG0]] : i8
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// CHECK-DAG: %[[H0:.*]] = sim.fmt.hex %[[ARG0]] : i8
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// CHECK-DAG: %[[B1:.*]] = sim.fmt.bin %[[ARG1]] : i8
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// CHECK-DAG: %[[H1:.*]] = sim.fmt.hex %[[ARG1]] : i8
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// CHECK-DAG: %[[B2:.*]] = sim.fmt.bin %[[ARG2]] : i8
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// CHECK-DAG: %[[H2:.*]] = sim.fmt.hex %[[ARG2]] : i8
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// CHECK-DAG: %[[CAT:.*]] = sim.fmt.concat (%[[B0]], %[[B1]], %[[B2]], %[[COM]], %[[H0]], %[[H1]], %[[H2]])
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// CHECK: sim.proc.print %[[CAT]]
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// CHECK-NEXT: }
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hw.module @multi_args(in %clk : !seq.clock, in %a: i8, in %b: i8, in %c: i8) {
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%true = hw.constant true
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%comma = sim.fmt.lit ", "
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%bina = sim.fmt.bin %a : i8
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%binb = sim.fmt.bin %b : i8
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%binc = sim.fmt.bin %c : i8
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%hexa = sim.fmt.hex %a : i8
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%hexb = sim.fmt.hex %b : i8
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%hexc = sim.fmt.hex %c : i8
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%cat = sim.fmt.concat (%bina, %binb, %binc, %comma, %hexa, %hexb, %hexc)
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sim.print %cat on %clk if %true
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}
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// CHECK-LABEL: @multi_clock
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// CHECK-NEXT: %[[TRGA:.*]] = seq.from_clock %clka
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// CHECK-NEXT: hw.triggered posedge %[[TRGA]](%val) : i32 {
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// CHECK-NEXT: ^bb0(%[[ARGA:.*]]: i32):
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// CHECK-DAG: %[[LA0:.*]] = sim.fmt.lit "Val is 0x"
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// CHECK-DAG: %[[LA1:.*]] = sim.fmt.lit " on A."
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// CHECK-DAG: %[[FA:.*]] = sim.fmt.hex %[[ARGA]] : i32
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// CHECK-DAG: %[[CATA:.*]] = sim.fmt.concat (%[[LA0]], %[[FA]], %[[LA1]])
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// CHECK: sim.proc.print %[[CATA]]
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// CHECK-NEXT: }
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// CHECK-NEXT: %[[TRGB:.*]] = seq.from_clock %clkb
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// CHECK-NEXT: hw.triggered posedge %[[TRGB]](%val) : i32 {
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// CHECK-NEXT: ^bb0(%[[ARGB:.*]]: i32):
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// CHECK-DAG: %[[LB0:.*]] = sim.fmt.lit "Val is 0x"
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// CHECK-DAG: %[[LB1:.*]] = sim.fmt.lit " on B."
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// CHECK-DAG: %[[FB:.*]] = sim.fmt.hex %[[ARGB]] : i32
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// CHECK-DAG: %[[CATB:.*]] = sim.fmt.concat (%[[LB0]], %[[FB]], %[[LB1]])
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// CHECK: sim.proc.print %[[CATB]]
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// CHECK-NEXT: }
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// CHECK-NEXT: %[[TRGC:.*]] = seq.from_clock %clkc
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// CHECK-NEXT: hw.triggered posedge %[[TRGC]](%val) : i32 {
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// CHECK-NEXT: ^bb0(%[[ARGC:.*]]: i32):
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// CHECK-DAG: %[[LC0:.*]] = sim.fmt.lit "Val is 0x"
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// CHECK-DAG: %[[LC1:.*]] = sim.fmt.lit " on C."
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// CHECK-DAG: %[[FC:.*]] = sim.fmt.hex %[[ARGC]] : i32
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// CHECK-DAG: %[[CATC:.*]] = sim.fmt.concat (%[[LC0]], %[[FC]], %[[LC1]])
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// CHECK: sim.proc.print %[[CATC]]
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// CHECK-NEXT: }
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hw.module @multi_clock(in %clka : !seq.clock, in %clkb : !seq.clock, in %clkc : !seq.clock, in %val: i32) {
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%true = hw.constant true
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%pre = sim.fmt.lit "Val is 0x"
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%hex_val = sim.fmt.hex %val : i32
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%onA = sim.fmt.lit " on A."
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%onB = sim.fmt.lit " on B."
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%onC = sim.fmt.lit " on C."
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%catA = sim.fmt.concat (%pre, %hex_val, %onA)
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sim.print %catA on %clka if %true
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%catB = sim.fmt.concat (%pre, %hex_val, %onB)
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sim.print %catB on %clkb if %true
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%catC = sim.fmt.concat (%pre, %hex_val, %onC)
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sim.print %catC on %clkc if %true
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}
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// CHECK-LABEL: @sequence
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// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
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// CHECK-NEXT: hw.triggered posedge %[[TRG]](%conda, %condb, %val) : i1, i1, i32 {
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// CHECK-NEXT: ^bb0(%[[ARG0:.*]]: i1, %[[ARG1:.*]]: i1, %[[ARG2:.*]]: i32):
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// CHECK-DAG: %[[L1:.*]] = sim.fmt.lit "#1"
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// CHECK-DAG: %[[L2:.*]] = sim.fmt.lit "#2"
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// CHECK-DAG: %[[L3:.*]] = sim.fmt.lit "#3"
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// CHECK-DAG: %[[L4:.*]] = sim.fmt.lit "#4"
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// CHECK-DAG: %[[L5:.*]] = sim.fmt.lit "#5"
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// CHECK-DAG: %[[L6:.*]] = sim.fmt.lit "#6"
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// CHECK-DAG: %[[BIN:.*]] = sim.fmt.bin %[[ARG2]] : i32
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// CHECK: scf.if %[[ARG0]] {
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// CHECK-NEXT: sim.proc.print %[[L1]]
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// CHECK-NEXT: }
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// CHECK-NEXT: scf.if %[[ARG1]] {
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// CHECK-NEXT: sim.proc.print %[[L2]]
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// CHECK-NEXT: sim.proc.print %[[L3]]
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// CHECK-NEXT: sim.proc.print %[[L4]]
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// CHECK-NEXT: }
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// CHECK-NEXT: scf.if %[[ARG0]] {
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// CHECK-NEXT: sim.proc.print %[[L5]]
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// CHECK-NEXT: }
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// CHECK-NEXT: sim.proc.print %[[BIN]]
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// CHECK-NEXT: scf.if %[[ARG0]] {
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// CHECK-NEXT: sim.proc.print %[[L6]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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hw.module @sequence(in %clk: !seq.clock, in %conda: i1, in %condb: i1, in %val : i32) {
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%true = hw.constant true
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%false = hw.constant false
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%1 = sim.fmt.lit "#1"
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sim.print %1 on %clk if %conda
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%2 = sim.fmt.lit "#2"
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sim.print %2 on %clk if %condb
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%3 = sim.fmt.lit "#3"
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sim.print %3 on %clk if %condb
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%cdis = sim.fmt.lit "--"
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sim.print %cdis on %clk if %false
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%4 = sim.fmt.lit "#4"
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sim.print %4 on %clk if %condb
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%5 = sim.fmt.lit "#5"
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sim.print %5 on %clk if %conda
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%cen = sim.fmt.bin %val : i32
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sim.print %cen on %clk if %true
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%6 = sim.fmt.lit "#6"
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sim.print %6 on %clk if %conda
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}
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// CHECK-LABEL: @condition_as_val
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// CHECK-NEXT: %[[TRG:.*]] = seq.from_clock %clk
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// CHECK-NEXT: hw.triggered posedge %[[TRG]](%condval) : i1 {
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// CHECK-NEXT: ^bb0(%[[ARG:.*]]: i1):
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// CHECK-NEXT: %[[BIN:.*]] = sim.fmt.bin %[[ARG]] : i1
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// CHECK-NEXT: scf.if %[[ARG]] {
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// CHECK-NEXT: sim.proc.print %[[BIN]]
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// CHECK-NEXT: }
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// CHECK-NEXT: }
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hw.module @condition_as_val(in %clk: !seq.clock, in %condval: i1) {
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%bin = sim.fmt.bin %condval : i1
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sim.print %bin on %clk if %condval
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}
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