mirror of https://github.com/llvm/circt.git
90 lines
3.5 KiB
MLIR
90 lines
3.5 KiB
MLIR
// RUN: circt-opt --lower-seq-to-sv %s | FileCheck %s
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// RUN: circt-opt --lower-seq-to-sv --export-verilog %s -o /dev/null | FileCheck %s --check-prefix=VERILOG
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// VERILOG-LABEL: module divide_by_0
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// CHECK-LABEL: @divide_by_0
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hw.module @divide_by_0(in %clock: !seq.clock, out by_2: !seq.clock) {
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// CHECK: hw.output %clock : i1
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%by_2 = seq.clock_div %clock by 0
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hw.output %by_2 : !seq.clock
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}
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// VERILOG-LABEL: module divide_by_2
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// CHECK-LABEL: @divide_by_2
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hw.module @divide_by_2(in %clock: !seq.clock, out by_2: !seq.clock) {
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// CHECK: [[REGISTER:%.+]] = sv.reg
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// CHECK: sv.always posedge %clock {
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// CHECK: [[READ_ALWAYS:%.+]] = sv.read_inout [[REGISTER]] : !hw.inout<i1>
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// CHECK: [[INVERTED:%.+]] = comb.xor [[READ_ALWAYS]], %true : i1
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// CHECK: sv.bpassign [[REGISTER]], [[INVERTED]] : i1
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// CHECK: }
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// CHECK: [[READ_OUTPUT:%.+]] = sv.read_inout [[REGISTER]] : !hw.inout<i1>
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// CHECK: sv.initial {
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// CHECK: sv.bpassign [[REGISTER]], %false : i1
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// CHECK: }
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// CHECK: hw.output [[READ_OUTPUT]] : i1
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// VERILOG: reg clock_out_0;
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// VERILOG: always @(posedge clock)
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// VERILOG: clock_out_0 = ~clock_out_0;
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// VERILOG: assign by_2 = clock_out_0;
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%by_2 = seq.clock_div %clock by 1
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hw.output %by_2 : !seq.clock
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}
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// VERILOG-LABEL: module divide_by_8
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// CHECK-LABEL: @divide_by_8
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hw.module @divide_by_8(in %clock: !seq.clock, out by_8: !seq.clock) {
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// CHECK: [[REGISTER_0:%.+]] = sv.reg : !hw.inout<i1>
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// CHECK: sv.always posedge %clock {
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// CHECK: [[REGISTER_0_READ:%.+]] = sv.read_inout [[REGISTER_0]] : !hw.inout<i1>
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// CHECK: [[INVERTED_0:%.+]] = comb.xor [[REGISTER_0_READ]], %true : i1
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// CHECK: sv.bpassign [[REGISTER_0]], [[INVERTED_0]] : i1
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// CHECK: }
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// CHECK: [[REGISTER_0_OUT:%.+]] = sv.read_inout [[REGISTER_0]] : !hw.inout<i1>
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// CHECK: [[REGISTER_1:%.+]] = sv.reg : !hw.inout<i1>
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// CHECK: sv.always posedge [[REGISTER_0_OUT]] {
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// CHECK: [[REGISTER_1_READ:%.+]] = sv.read_inout [[REGISTER_1]] : !hw.inout<i1>
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// CHECK: [[INVERTED_1:%.+]] = comb.xor [[REGISTER_1_READ]], %true : i1
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// CHECK: sv.bpassign [[REGISTER_1]], [[INVERTED_1]] : i1
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// CHECK: }
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// CHECK: [[REGISTER_1_OUT:%.+]] = sv.read_inout [[REGISTER_1]] : !hw.inout<i1>
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// CHECK: [[REGISTER_2:%.+]] = sv.reg : !hw.inout<i1>
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// CHECK: sv.always posedge [[REGISTER_1_OUT]] {
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// CHECK: [[REGISTER_2_READ:%.+]] = sv.read_inout [[REGISTER_2]] : !hw.inout<i1>
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// CHECK: [[INVERTED_2:%.+]] = comb.xor [[REGISTER_2_READ]], %true : i1
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// CHECK: sv.bpassign [[REGISTER_2]], [[INVERTED_2]] : i1
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// CHECK: }
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// CHECK: [[REGISTER_2_OUT:%.+]] = sv.read_inout [[REGISTER_2]] : !hw.inout<i1>
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// CHECK: sv.initial {
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// CHECK: sv.bpassign [[REGISTER_0]], %false : i1
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// CHECK: sv.bpassign [[REGISTER_1]], %false : i1
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// CHECK: sv.bpassign [[REGISTER_2]], %false : i1
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// CHECK: }
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// CHECK: hw.output [[REGISTER_2_OUT]] : i1
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// VERILOG: reg clock_out_0;
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// VERILOG: always @(posedge clock)
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// VERILOG: clock_out_0 = ~clock_out_0;
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// VERILOG: reg clock_out_1;
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// VERILOG: always @(posedge clock_out_0)
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// VERILOG: clock_out_1 = ~clock_out_1;
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// VERILOG: reg clock_out_2;
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// VERILOG: always @(posedge clock_out_1)
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// VERILOG: clock_out_2 = ~clock_out_2;
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// VERILOG: initial begin
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// VERILOG: clock_out_0 = 1'h0;
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// VERILOG: clock_out_1 = 1'h0;
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// VERILOG: clock_out_2 = 1'h0;
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// VERILOG: end
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// VERILOG: assign by_8 = clock_out_2;
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%by_8 = seq.clock_div %clock by 3
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hw.output %by_8 : !seq.clock
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}
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