mirror of https://github.com/llvm/circt.git
229 lines
10 KiB
MLIR
229 lines
10 KiB
MLIR
// RUN: circt-opt %s --split-input-file --verify-diagnostics | FileCheck %s
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// CHECK-LABEL: @cpus
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// CHECK-SAME: !rtgtest.cpu
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rtg.target @cpus : !rtg.dict<cpu: !rtgtest.cpu> {
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// CHECK: rtgtest.cpu_decl <0>
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%0 = rtgtest.cpu_decl <0>
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rtg.yield %0 : !rtgtest.cpu
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}
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rtg.test @misc() {
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// CHECK: rtgtest.constant_test i32 {value = "str"}
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%0 = rtgtest.constant_test i32 {value = "str"}
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}
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// CHECK-LABEL: rtg.test @registers
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// CHECK-SAME: !rtgtest.ireg
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rtg.test @registers(reg = %reg: !rtgtest.ireg) {
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// CHECK: rtg.fixed_reg #rtgtest.zero : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.ra : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.sp : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.gp : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.tp : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.t0 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.t1 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.t2 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s0 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s1 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a0 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a1 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a2 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a3 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a4 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a5 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a6 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.a7 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s2 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s3 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s4 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s5 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s6 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s7 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s8 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s9 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s10 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.s11 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.t3 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.t4 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.t5 : !rtgtest.ireg
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// CHECK: rtg.fixed_reg #rtgtest.t6 : !rtgtest.ireg
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rtg.fixed_reg #rtgtest.zero
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rtg.fixed_reg #rtgtest.ra
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rtg.fixed_reg #rtgtest.sp
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rtg.fixed_reg #rtgtest.gp
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rtg.fixed_reg #rtgtest.tp
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rtg.fixed_reg #rtgtest.t0
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rtg.fixed_reg #rtgtest.t1
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rtg.fixed_reg #rtgtest.t2
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rtg.fixed_reg #rtgtest.s0
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rtg.fixed_reg #rtgtest.s1
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rtg.fixed_reg #rtgtest.a0
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rtg.fixed_reg #rtgtest.a1
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rtg.fixed_reg #rtgtest.a2
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rtg.fixed_reg #rtgtest.a3
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rtg.fixed_reg #rtgtest.a4
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rtg.fixed_reg #rtgtest.a5
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rtg.fixed_reg #rtgtest.a6
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rtg.fixed_reg #rtgtest.a7
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rtg.fixed_reg #rtgtest.s2
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rtg.fixed_reg #rtgtest.s3
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rtg.fixed_reg #rtgtest.s4
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rtg.fixed_reg #rtgtest.s5
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rtg.fixed_reg #rtgtest.s6
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rtg.fixed_reg #rtgtest.s7
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rtg.fixed_reg #rtgtest.s8
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rtg.fixed_reg #rtgtest.s9
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rtg.fixed_reg #rtgtest.s10
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rtg.fixed_reg #rtgtest.s11
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rtg.fixed_reg #rtgtest.t3
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rtg.fixed_reg #rtgtest.t4
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rtg.fixed_reg #rtgtest.t5
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rtg.fixed_reg #rtgtest.t6
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// CHECK: rtg.virtual_reg [#rtgtest.ra : !rtgtest.ireg, #rtgtest.sp : !rtgtest.ireg]
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rtg.virtual_reg [#rtgtest.ra, #rtgtest.sp]
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}
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// CHECK-LABEL: @immediates
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rtg.test @immediates() {
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// CHECK: rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5
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rtgtest.immediate #rtgtest.imm5<3> : !rtgtest.imm5
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// CHECK: rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12
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rtgtest.immediate #rtgtest.imm12<3> : !rtgtest.imm12
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// CHECK: rtgtest.immediate #rtgtest.imm13<3> : !rtgtest.imm13
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rtgtest.immediate #rtgtest.imm13<3> : !rtgtest.imm13
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// CHECK: rtgtest.immediate #rtgtest.imm21<3> : !rtgtest.imm21
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rtgtest.immediate #rtgtest.imm21<3> : !rtgtest.imm21
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// CHECK: rtgtest.immediate #rtgtest.imm32<3> : !rtgtest.imm32
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rtgtest.immediate #rtgtest.imm32<3> : !rtgtest.imm32
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}
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// CHECK-LABEL: @instructions
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// CHECK-SAME: (imm = [[IMM:%.+]]: !rtgtest.imm12, imm13 = [[IMM13:%.+]]: !rtgtest.imm13, imm21 = [[IMM21:%.+]]: !rtgtest.imm21, imm32 = [[IMM32:%.+]]: !rtgtest.imm32, imm5 = [[IMM5:%.+]]: !rtgtest.imm5, label = [[LABEL:%.+]]: !rtg.label, rd = [[RD:%.+]]: !rtgtest.ireg, rs = [[RS:%.+]]: !rtgtest.ireg)
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rtg.test @instructions(imm = %imm: !rtgtest.imm12, imm13 = %imm13: !rtgtest.imm13, imm21 = %imm21: !rtgtest.imm21, imm32 = %imm32: !rtgtest.imm32, imm5 = %imm5: !rtgtest.imm5, label = %label: !rtg.label, rd = %rd: !rtgtest.ireg, rs = %rs: !rtgtest.ireg) {
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// CHECK: rtgtest.rv32i.jalr [[RD]], [[RS]], [[IMM]]
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rtgtest.rv32i.jalr %rd, %rs, %imm
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// CHECK: rtgtest.rv32i.lb [[RD]], [[RS]], [[IMM]]
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rtgtest.rv32i.lb %rd, %rs, %imm
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// CHECK: rtgtest.rv32i.lh [[RD]], [[RS]], [[IMM]]
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rtgtest.rv32i.lh %rd, %rs, %imm
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// CHECK: rtgtest.rv32i.lw [[RD]], [[RS]], [[IMM]]
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rtgtest.rv32i.lw %rd, %rs, %imm
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// CHECK: rtgtest.rv32i.lbu [[RD]], [[RS]], [[IMM]]
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rtgtest.rv32i.lbu %rd, %rs, %imm
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// CHECK: rtgtest.rv32i.lhu [[RD]], [[RS]], [[IMM]]
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rtgtest.rv32i.lhu %rd, %rs, %imm
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// CHECK: rtgtest.rv32i.ecall
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rtgtest.rv32i.ecall
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// CHECK: rtgtest.rv32i.ebreak
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rtgtest.rv32i.ebreak
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// CHECK: rtgtest.rv32i.beq [[RD]], [[RS]], [[IMM13]] : !rtgtest.imm13
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rtgtest.rv32i.beq %rd, %rs, %imm13 : !rtgtest.imm13
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// CHECK: rtgtest.rv32i.bne [[RD]], [[RS]], [[IMM13]] : !rtgtest.imm13
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rtgtest.rv32i.bne %rd, %rs, %imm13 : !rtgtest.imm13
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// CHECK: rtgtest.rv32i.blt [[RD]], [[RS]], [[IMM13]] : !rtgtest.imm13
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rtgtest.rv32i.blt %rd, %rs, %imm13 : !rtgtest.imm13
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// CHECK: rtgtest.rv32i.bge [[RD]], [[RS]], [[IMM13]] : !rtgtest.imm13
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rtgtest.rv32i.bge %rd, %rs, %imm13 : !rtgtest.imm13
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// CHECK: rtgtest.rv32i.bltu [[RD]], [[RS]], [[IMM13]] : !rtgtest.imm13
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rtgtest.rv32i.bltu %rd, %rs, %imm13 : !rtgtest.imm13
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// CHECK: rtgtest.rv32i.bgeu [[RD]], [[RS]], [[IMM13]] : !rtgtest.imm13
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rtgtest.rv32i.bgeu %rd, %rs, %imm13 : !rtgtest.imm13
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// CHECK: rtgtest.rv32i.beq [[RD]], [[RS]], [[LABEL]] : !rtg.label
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rtgtest.rv32i.beq %rd, %rs, %label : !rtg.label
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// CHECK: rtgtest.rv32i.bne [[RD]], [[RS]], [[LABEL]] : !rtg.label
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rtgtest.rv32i.bne %rd, %rs, %label : !rtg.label
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// CHECK: rtgtest.rv32i.blt [[RD]], [[RS]], [[LABEL]] : !rtg.label
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rtgtest.rv32i.blt %rd, %rs, %label : !rtg.label
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// CHECK: rtgtest.rv32i.bge [[RD]], [[RS]], [[LABEL]] : !rtg.label
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rtgtest.rv32i.bge %rd, %rs, %label : !rtg.label
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// CHECK: rtgtest.rv32i.bltu [[RD]], [[RS]], [[LABEL]] : !rtg.label
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rtgtest.rv32i.bltu %rd, %rs, %label : !rtg.label
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// CHECK: rtgtest.rv32i.bgeu [[RD]], [[RS]], [[LABEL]] : !rtg.label
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rtgtest.rv32i.bgeu %rd, %rs, %label : !rtg.label
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// CHECK: rtgtest.rv32i.add [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.add %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sub [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.sub %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sll [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.sll %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.slt [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.slt %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sltu [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.sltu %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.xor [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.xor %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.srl [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.srl %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sra [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.sra %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.or [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.or %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.and [[RD]], [[RS]], [[RS]] {rtg.some_attr}
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rtgtest.rv32i.and %rd, %rs, %rs {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sb [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.sb %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sh [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.sh %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sw [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.sw %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.lui [[RD]], [[IMM32]] : !rtgtest.imm32 {rtg.some_attr}
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rtgtest.rv32i.lui %rd, %imm32 : !rtgtest.imm32 {rtg.some_attr}
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// CHECK: rtgtest.rv32i.auipc [[RD]], [[IMM32]] : !rtgtest.imm32 {rtg.some_attr}
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rtgtest.rv32i.auipc %rd, %imm32 : !rtgtest.imm32 {rtg.some_attr}
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// CHECK: rtgtest.rv32i.jal [[RD]], [[IMM21]] : !rtgtest.imm21 {rtg.some_attr}
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rtgtest.rv32i.jal %rd, %imm21 : !rtgtest.imm21 {rtg.some_attr}
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// CHECK: rtgtest.rv32i.lui [[RD]], [[LABEL]] : !rtg.label {rtg.some_attr}
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rtgtest.rv32i.lui %rd, %label : !rtg.label {rtg.some_attr}
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// CHECK: rtgtest.rv32i.auipc [[RD]], [[LABEL]] : !rtg.label {rtg.some_attr}
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rtgtest.rv32i.auipc %rd, %label : !rtg.label {rtg.some_attr}
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// CHECK: rtgtest.rv32i.jal [[RD]], [[LABEL]] : !rtg.label {rtg.some_attr}
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rtgtest.rv32i.jal %rd, %label : !rtg.label {rtg.some_attr}
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// CHECK: rtgtest.rv32i.addi [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.addi %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.slti [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.slti %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.sltiu [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.sltiu %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.xori [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.xori %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.ori [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.ori %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.andi [[RD]], [[RS]], [[IMM]] {rtg.some_attr}
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rtgtest.rv32i.andi %rd, %rs, %imm {rtg.some_attr}
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// CHECK: rtgtest.rv32i.slli [[RD]], [[RS]], [[IMM5]] {rtg.some_attr}
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rtgtest.rv32i.slli %rd, %rs, %imm5 {rtg.some_attr}
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// CHECK: rtgtest.rv32i.srli [[RD]], [[RS]], [[IMM5]] {rtg.some_attr}
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rtgtest.rv32i.srli %rd, %rs, %imm5 {rtg.some_attr}
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// CHECK: rtgtest.rv32i.srai [[RD]], [[RS]], [[IMM5]] {rtg.some_attr}
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rtgtest.rv32i.srai %rd, %rs, %imm5 {rtg.some_attr}
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}
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// -----
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rtg.test @immediateTooBig() {
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// expected-error @below {{cannot represent 2000000 with 12 bits}}
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rtgtest.immediate #rtgtest.imm12<2000000> : !rtgtest.imm12
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}
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// -----
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rtg.test @emptyAllowed() {
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// expected-error @below {{must have at least one allowed register}}
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rtg.virtual_reg []
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}
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// -----
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rtg.test @invalidAllowedAttr() {
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// expected-error @below {{allowed register attributes must be of RegisterAttrInterface}}
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rtg.virtual_reg ["invalid"]
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}
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