mirror of https://github.com/llvm/circt.git
116 lines
3.6 KiB
MLIR
116 lines
3.6 KiB
MLIR
// RUN: circt-opt --rtg-inline-sequences --split-input-file --verify-diagnostics %s | FileCheck %s
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// CHECK-NOT: rtg.sequence
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rtg.sequence @seq0() {
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rtgtest.rv32i.ebreak
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rtgtest.rv32i.ebreak
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}
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rtg.sequence @seq1() {
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rtgtest.rv32i.ecall
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rtgtest.rv32i.ecall
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}
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// CHECK-LABEL: @inlineSequences
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rtg.test @inlineSequences() {
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// CHECK-NEXT: rtgtest.rv32i.ecall
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ecall
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// CHECK-NEXT: }
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%0 = rtg.get_sequence @seq0 : !rtg.sequence
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%1 = rtg.randomize_sequence %0
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rtgtest.rv32i.ecall
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rtg.embed_sequence %1
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rtgtest.rv32i.ecall
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}
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// CHECK-LABEL: @interleaveSequences
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rtg.test @interleaveSequences() {
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%0 = rtg.get_sequence @seq0 : !rtg.sequence
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%1 = rtg.get_sequence @seq1 : !rtg.sequence
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%2 = rtg.randomize_sequence %0
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%3 = rtg.randomize_sequence %1
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ecall
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// CHECK-NEXT: rtgtest.rv32i.ecall
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%4 = rtg.interleave_sequences %2, %3 batch 2
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rtg.embed_sequence %4
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ecall
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ecall
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%5 = rtg.interleave_sequences %2, %3
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rtg.embed_sequence %5
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ecall
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// CHECK-NEXT: rtgtest.rv32i.ecall
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// CHECK-NEXT: rtgtest.rv32i.ecall
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// CHECK-NEXT: rtgtest.rv32i.ebreak
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// CHECK-NEXT: rtgtest.rv32i.ecall
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%6 = rtg.interleave_sequences %2, %3
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%7 = rtg.interleave_sequences %6, %3
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rtg.embed_sequence %7
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// CHECK-NEXT: }
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}
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rtg.sequence @nested0() {
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%ra = rtg.fixed_reg #rtgtest.ra
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%sp = rtg.fixed_reg #rtgtest.s0
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%imm = rtgtest.immediate #rtgtest.imm12<1>
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rtgtest.rv32i.jalr %ra, %sp, %imm
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}
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rtg.sequence @nested1() {
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%0 = rtg.get_sequence @nested0 : !rtg.sequence
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%1 = rtg.randomize_sequence %0
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rtg.embed_sequence %1
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%ra = rtg.fixed_reg #rtgtest.ra
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%sp = rtg.fixed_reg #rtgtest.sp
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%imm = rtgtest.immediate #rtgtest.imm12<0>
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rtgtest.rv32i.jalr %ra, %sp, %imm
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}
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// CHECK-LABEL: @nestedSequences()
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rtg.test @nestedSequences() {
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// CHECK-NEXT: [[RA0:%.+]] = rtg.fixed_reg #rtgtest.ra : !rtgtest.ireg
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// CHECK-NEXT: [[S0:%.+]] = rtg.fixed_reg #rtgtest.s0 : !rtgtest.ireg
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// CHECK-NEXT: [[IMM1:%.+]] = rtgtest.immediate #rtgtest.imm12<1> : !rtgtest.imm12
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// CHECK-NEXT: rtgtest.rv32i.jalr [[RA0]], [[S0]], [[IMM1]]
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// CHECK-NEXT: [[RA1:%.+]] = rtg.fixed_reg #rtgtest.ra : !rtgtest.ireg
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// CHECK-NEXT: [[SP:%.+]] = rtg.fixed_reg #rtgtest.sp : !rtgtest.ireg
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// CHECK-NEXT: [[IMM0:%.+]] = rtgtest.immediate #rtgtest.imm12<0> : !rtgtest.imm12
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// CHECK-NEXT: rtgtest.rv32i.jalr [[RA1]], [[SP]], [[IMM0]]
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%0 = rtg.get_sequence @nested1 : !rtg.sequence
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%1 = rtg.randomize_sequence %0
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rtg.embed_sequence %1
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}
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// -----
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rtg.test @test0(seq = %seq : !rtg.randomized_sequence) {
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// expected-error @below {{sequence operand could not be resolved; it was likely produced by an op or block argument not supported by this pass}}
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rtg.embed_sequence %seq
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}
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// -----
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rtg.test @test0(seq = %seq : !rtg.sequence) {
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// expected-error @below {{sequence operand could not be resolved; it was likely produced by an op or block argument not supported by this pass}}
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%0 = rtg.randomize_sequence %seq
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rtg.embed_sequence %0
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}
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// -----
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rtg.test @test0(seq0 = %seq0 : !rtg.randomized_sequence, seq1 = %seq1 : !rtg.randomized_sequence) {
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// expected-error @below {{sequence operand #0 could not be resolved; it was likely produced by an op or block argument not supported by this pass}}
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%0 = rtg.interleave_sequences %seq0, %seq1
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rtg.embed_sequence %0
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}
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