mirror of https://github.com/llvm/circt.git
176 lines
8.3 KiB
MLIR
176 lines
8.3 KiB
MLIR
// RUN: circt-opt %s -verify-diagnostics | circt-opt -verify-diagnostics | FileCheck %s
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// CHECK-LABEL: hw.module @unscheduled1
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// CHECK-NEXT: %out, %done = pipeline.unscheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: %0 = pipeline.latency 2 -> (i32) {
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// CHECK-NEXT: %1 = comb.add %a0, %a1 : i32
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// CHECK-NEXT: pipeline.latency.return %1 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: pipeline.return %0 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @unscheduled1(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.unscheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
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%0 = pipeline.latency 2 -> (i32) {
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%1 = comb.add %a0, %a1 : i32
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pipeline.latency.return %1 : i32
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}
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pipeline.return %0 : i32
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}
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hw.output %0 : i32
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}
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// CHECK-LABEL: hw.module @scheduled1
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// CHECK-NEXT: %out, %done = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: %0 = comb.add %a0, %a1 : i32
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// CHECK-NEXT: pipeline.stage ^bb1
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// CHECK-NEXT: ^bb1(%s1_enable: i1): // pred: ^bb0
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// CHECK-NEXT: pipeline.return %0 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @scheduled1(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
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%0 = comb.add %a0, %a1 : i32
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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pipeline.return %0 : i32
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}
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hw.output %0 : i32
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}
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// CHECK-LABEL: hw.module @scheduled2
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// CHECK-NEXT: %out, %done = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: %0 = comb.add %a0, %a1 : i32
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// CHECK-NEXT: pipeline.stage ^bb1 regs(%0 : i32)
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// CHECK-NEXT: ^bb1(%s1_reg0: i32, %s1_enable: i1): // pred: ^bb0
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// CHECK-NEXT: pipeline.return %s1_reg0 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @scheduled2(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%0 = comb.add %a0, %a1 : i32
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pipeline.stage ^bb1 regs(%0 : i32)
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^bb1(%s0_0 : i32, %s1_enable : i1):
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pipeline.return %s0_0 : i32
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}
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hw.output %0 : i32
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}
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// CHECK-LABEL: hw.module @scheduledWithPassthrough
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// CHECK-NEXT: %out0, %out1, %done = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out0 : i32, out1 : i32) {
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// CHECK-NEXT: %0 = comb.add %a0, %a1 : i32
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// CHECK-NEXT: pipeline.stage ^bb1 regs(%0 : i32) pass(%a1 : i32)
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// CHECK-NEXT: ^bb1(%s1_reg0: i32, %s1_pass0: i32, %s1_enable: i1): // pred: ^bb0
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// CHECK-NEXT: pipeline.return %s1_reg0, %s1_pass0 : i32, i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out0 : i32
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// CHECK-NEXT: }
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hw.module @scheduledWithPassthrough(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:3 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out0: i32, out1: i32) {
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%0 = comb.add %a0, %a1 : i32
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pipeline.stage ^bb1 regs(%0 : i32) pass(%a1 : i32)
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^bb1(%s0_0 : i32, %s0_pass_a1 : i32, %s1_enable : i1):
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pipeline.return %s0_0, %s0_pass_a1 : i32, i32
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}
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hw.output %0#0 : i32
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}
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// CHECK-LABEL: hw.module @withStall
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// CHECK-NEXT: %out, %done = pipeline.scheduled(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: pipeline.return %a0 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @withStall(in %arg0 : i32, in %stall : i1, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.scheduled(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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pipeline.return %a0 : i32
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}
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hw.output %0 : i32
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}
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// CHECK-LABEL: hw.module @withMultipleRegs
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// CHECK-NEXT: %out, %done = pipeline.scheduled(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: pipeline.stage ^bb1 regs(%a0 : i32, %a0 : i32)
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// CHECK-NEXT: ^bb1(%s1_reg0: i32, %s1_reg1: i32, %s1_enable: i1): // pred: ^bb0
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// CHECK-NEXT: pipeline.return %s1_reg0 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @withMultipleRegs(in %arg0 : i32, in %stall : i1, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.scheduled(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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pipeline.stage ^bb1 regs(%a0 : i32, %a0 : i32)
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^bb1(%0 : i32, %1 : i32, %s1_enable : i1):
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pipeline.return %0 : i32
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}
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hw.output %0 : i32
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}
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// CHECK-LABEL: hw.module @withClockGates
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// CHECK-NEXT: %out, %done = pipeline.scheduled(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: %true = hw.constant true
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// CHECK-NEXT: %true_0 = hw.constant true
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// CHECK-NEXT: %true_1 = hw.constant true
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// CHECK-NEXT: pipeline.stage ^bb1 regs(%a0 : i32 gated by [%true], %a0 : i32, %a0 : i32 gated by [%true_0, %true_1])
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// CHECK-NEXT: ^bb1(%s1_reg0: i32, %s1_reg1: i32, %s1_reg2: i32, %s1_enable: i1): // pred: ^bb0
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// CHECK-NEXT: pipeline.return %s1_reg0 : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @withClockGates(in %arg0 : i32, in %stall : i1, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.scheduled(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%true1 = hw.constant true
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%true2 = hw.constant true
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%true3 = hw.constant true
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pipeline.stage ^bb1 regs(%a0 : i32 gated by [%true1], %a0 : i32, %a0 : i32 gated by [%true2, %true3])
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^bb1(%0 : i32, %1 : i32, %2 : i32, %s1_enable : i1):
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pipeline.return %0 : i32
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}
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hw.output %0 : i32
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}
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// CHECK-LABEL: hw.module @withNames
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// CHECK-NEXT: %out, %done = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: %0 = comb.add %a0, %a1 : i32
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// CHECK-NEXT: pipeline.stage ^bb1 regs("myAdd" = %0 : i32, %0 : i32, "myOtherAdd" = %0 : i32)
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// CHECK-NEXT: ^bb1(%myAdd: i32, %s1_reg1: i32, %myOtherAdd: i32, %s1_enable: i1): // pred: ^bb0
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// CHECK-NEXT: pipeline.return %myAdd : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @withNames(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
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%0 = comb.add %a0, %a1 : i32
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pipeline.stage ^bb1 regs("myAdd" = %0 : i32, %0 : i32, "myOtherAdd" = %0 : i32)
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^bb1(%r1 : i32, %r2 : i32, %r3 : i32, %s1_enable : i1):
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pipeline.return %r1 : i32
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}
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hw.output %0 : i32
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}
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// CHECK-LABEL: hw.module @withStallability
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// CHECK: %out, %done = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) {stallability = [true, false, true]} -> (out : i32)
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hw.module @withStallability(in %arg0 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, in %stall : i1, out out: i32) {
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%0:2 = pipeline.scheduled "MyPipeline"(%a0 : i32 = %arg0) stall(%stall) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable)
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{stallability = [true, false, true]}
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-> (out: i32) {
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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pipeline.stage ^bb3
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^bb3(%s3_enable : i1):
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pipeline.return %a0 : i32
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}
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hw.output %0 : i32
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}
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