mirror of https://github.com/llvm/circt.git
47 lines
2.4 KiB
MLIR
47 lines
2.4 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(any(pipeline-schedule-linear))' %s | FileCheck %s
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// CHECK-LABEL: hw.module @pipeline(
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// CHECK-SAME: in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[GO:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[RESET:.*]] : i1, out out : i32) {
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// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = pipeline.scheduled(%[[VAL_7:.*]] : i32 = %[[VAL_0]], %[[VAL_8:.*]] : i32 = %[[VAL_1]]) clock(%[[CLOCK]]) reset(%[[RESET]]) go(%[[GO]]) entryEn(%[[VAL_9:.*]]) -> (out : i32) {
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// CHECK: %[[VAL_10:.*]] = comb.add %[[VAL_7]], %[[VAL_8]] {ssp.operator_type = @add1} : i32
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// CHECK: %[[VAL_11:.*]] = comb.add %[[VAL_8]], %[[VAL_7]] {ssp.operator_type = @add1} : i32
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// CHECK: pipeline.stage ^bb1
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// CHECK: ^bb1(%[[VAL_12:.*]]: i1):
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// CHECK: pipeline.stage ^bb2
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// CHECK: ^bb2(%[[VAL_13:.*]]: i1):
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// CHECK: %[[VAL_14:.*]] = comb.mul %[[VAL_7]], %[[VAL_10]] {ssp.operator_type = @mul2} : i32
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// CHECK: pipeline.stage ^bb3
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// CHECK: ^bb3(%[[VAL_15:.*]]: i1):
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// CHECK: pipeline.stage ^bb4
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// CHECK: ^bb4(%[[VAL_16:.*]]: i1):
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// CHECK: pipeline.stage ^bb5
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// CHECK: ^bb5(%[[VAL_17:.*]]: i1):
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// CHECK: %[[VAL_18:.*]] = comb.add %[[VAL_14]], %[[VAL_11]] {ssp.operator_type = @add1} : i32
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// CHECK: pipeline.stage ^bb6
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// CHECK: ^bb6(%[[VAL_19:.*]]: i1):
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// CHECK: pipeline.stage ^bb7
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// CHECK: ^bb7(%[[VAL_20:.*]]: i1):
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// CHECK: pipeline.return %[[VAL_18]] : i32
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// CHECK: }
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// CHECK: hw.output %[[VAL_21:.*]] : i32
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// CHECK: }
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module {
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ssp.library @lib {
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operator_type @add1 [latency<2>]
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operator_type @mul2 [latency<3>]
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}
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hw.module @pipeline(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%0:2 = pipeline.unscheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable)
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{operator_lib = @lib} -> (out: i32) {
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%0 = comb.add %a0, %a1 {ssp.operator_type = @add1} : i32
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%1 = comb.mul %a0, %0 {ssp.operator_type = @mul2} : i32
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%2 = comb.add %a1, %a0 {ssp.operator_type = @add1} : i32
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%3 = comb.add %1, %2 {ssp.operator_type = @add1} : i32
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pipeline.return %3 : i32
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}
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hw.output %0#0 : i32
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}
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}
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