mirror of https://github.com/llvm/circt.git
328 lines
16 KiB
MLIR
328 lines
16 KiB
MLIR
// RUN: circt-opt -pipeline-explicit-regs --allow-unregistered-dialect %s | FileCheck %s
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// CHECK-LABEL: hw.module @testRegsOnly(
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// CHECK-SAME: in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[GO:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[RESET:.*]] : i1, out out0 : i32, out out1 : i1) {
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// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = pipeline.scheduled(%[[VAL_7:.*]] : i32 = %[[VAL_0]], %[[VAL_8:.*]] : i32 = %[[VAL_1]]) clock(%[[CLOCK]]) reset(%[[RESET]]) go(%[[GO]]) entryEn(%[[S0_VALID:.*]]) -> (out : i32) {
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// CHECK: %[[VAL_12:.*]] = comb.add %[[VAL_7]], %[[VAL_8]] : i32
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// CHECK: pipeline.stage ^bb1 regs(%[[VAL_12]] : i32, "a0" = %[[VAL_7]] : i32)
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// CHECK: ^bb1(%[[VAL_13:.*]]: i32, %[[VAL_14:.*]]: i32, %[[VAL_15:.*]]: i1):
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// CHECK: %[[VAL_16:.*]] = comb.add %[[VAL_13]], %[[VAL_14]] : i32
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// CHECK: pipeline.stage ^bb2 regs(%[[VAL_16]] : i32, %[[VAL_13]] : i32)
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// CHECK: ^bb2(%[[VAL_17:.*]]: i32, %[[VAL_18:.*]]: i32, %[[VAL_19:.*]]: i1):
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// CHECK: %[[VAL_20:.*]] = comb.add %[[VAL_17]], %[[VAL_18]] : i32
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// CHECK: pipeline.return %[[VAL_20]] : i32
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// CHECK: }
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// CHECK: hw.output %[[VAL_21:.*]], %[[VAL_22:.*]] : i32, i1
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// CHECK: }
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hw.module @testRegsOnly(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out0: i32, out out1: i1) {
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%out:2 = pipeline.scheduled(%a0 : i32 = %arg0, %a1 : i32 = %arg1) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32){
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%add0 = comb.add %a0, %a1 : i32
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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%add1 = comb.add %add0, %a0 : i32 // %a0 is a block argument fed through a stage.
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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%add2 = comb.add %add1, %add0 : i32 // %add0 crosses multiple stages.
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pipeline.return %add2 : i32
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}
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hw.output %out#0, %out#1 : i32, i1
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}
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// CHECK-LABEL: hw.module @testLatency1(
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// CHECK-SAME: in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[GO:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[RESET:.*]] : i1, out out : i32) {
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// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = pipeline.scheduled(%[[VAL_7:.*]] : i32 = %[[VAL_0]]) clock(%[[CLOCK]]) reset(%[[RESET]]) go(%[[GO]]) entryEn(%[[S0_VALID:.*]]) -> (out : i32) {
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// CHECK: %[[VAL_11:.*]] = hw.constant true
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// CHECK: %[[VAL_12:.*]] = pipeline.latency 2 -> (i32) {
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// CHECK: %[[VAL_13:.*]] = comb.add %[[VAL_7]], %[[VAL_7]] : i32
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// CHECK: pipeline.latency.return %[[VAL_13]] : i32
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// CHECK: }
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// CHECK: pipeline.stage ^bb1 pass(%[[VAL_12]] : i32)
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// CHECK: ^bb1(%[[VAL_14:.*]]: i32, %[[VAL_15:.*]]: i1):
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// CHECK: pipeline.stage ^bb2 pass(%[[VAL_14]] : i32)
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// CHECK: ^bb2(%[[VAL_16:.*]]: i32, %[[VAL_17:.*]]: i1):
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// CHECK: pipeline.stage ^bb3 regs(%[[VAL_16]] : i32)
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// CHECK: ^bb3(%[[VAL_18:.*]]: i32, %[[VAL_19:.*]]: i1):
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// CHECK: pipeline.stage ^bb4 regs(%[[VAL_18]] : i32)
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// CHECK: ^bb4(%[[VAL_20:.*]]: i32, %[[VAL_21:.*]]: i1):
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// CHECK: pipeline.return %[[VAL_20]] : i32
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// CHECK: }
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// CHECK: hw.output %[[VAL_23:.*]] : i32
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// CHECK: }
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hw.module @testLatency1(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%out:2 = pipeline.scheduled(%a0 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%true = hw.constant true
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%out = pipeline.latency 2 -> (i32) {
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%d = comb.add %a0, %a0 : i32
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pipeline.latency.return %d : i32
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}
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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pipeline.stage ^bb3
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^bb3(%s3_enable : i1):
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pipeline.stage ^bb4
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^bb4(%s4_enable : i1):
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pipeline.return %out : i32
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}
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hw.output %out#0 : i32
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}
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// CHECK-LABEL: hw.module @testLatency2(
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// CHECK-SAME: in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[GO:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[RESET:.*]] : i1, out out : i32) {
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// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = pipeline.scheduled(%[[VAL_7:.*]] : i32 = %[[VAL_0]]) clock(%[[CLOCK]]) reset(%[[RESET]]) go(%[[GO]]) entryEn(%[[S0_VALID:.*]]) -> (out : i32) {
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// CHECK: %[[VAL_11:.*]] = hw.constant true
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// CHECK: %[[VAL_12:.*]] = pipeline.latency 1 -> (i32) {
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// CHECK: %[[VAL_13:.*]] = comb.add %[[VAL_7]], %[[VAL_7]] : i32
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// CHECK: pipeline.latency.return %[[VAL_13]] : i32
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// CHECK: }
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// CHECK: pipeline.stage ^bb1 pass(%[[VAL_14:.*]] : i32)
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// CHECK: ^bb1(%[[VAL_15:.*]]: i32, %[[VAL_16:.*]]: i1):
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// CHECK: pipeline.stage ^bb2 regs(%[[VAL_15]] : i32)
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// CHECK: ^bb2(%[[VAL_17:.*]]: i32, %[[VAL_18:.*]]: i1):
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// CHECK: %[[VAL_19:.*]] = pipeline.latency 2 -> (i32) {
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// CHECK: %[[VAL_20:.*]] = comb.sub %[[VAL_17]], %[[VAL_17]] : i32
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// CHECK: pipeline.latency.return %[[VAL_20]] : i32
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// CHECK: }
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// CHECK: pipeline.stage ^bb3 regs(%[[VAL_17]] : i32) pass(%[[VAL_21:.*]] : i32)
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// CHECK: ^bb3(%[[VAL_22:.*]]: i32, %[[VAL_23:.*]]: i32, %[[VAL_24:.*]]: i1):
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// CHECK: pipeline.stage ^bb4 regs(%[[VAL_22]] : i32) pass(%[[VAL_23]] : i32)
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// CHECK: ^bb4(%[[VAL_25:.*]]: i32, %[[VAL_26:.*]]: i32, %[[VAL_27:.*]]: i1):
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// CHECK: %[[VAL_28:.*]] = comb.add %[[VAL_25]], %[[VAL_26]] : i32
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// CHECK: pipeline.return %[[VAL_25]] : i32
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// CHECK: }
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// CHECK: hw.output %[[VAL_29:.*]] : i32
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// CHECK: }
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hw.module @testLatency2(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out : i32) {
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%out:2 = pipeline.scheduled(%a0 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%true = hw.constant true
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%out = pipeline.latency 1 -> (i32) {
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%d = comb.add %a0, %a0 : i32
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pipeline.latency.return %d : i32
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}
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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%out2 = pipeline.latency 2 -> (i32) {
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%d = comb.sub %out, %out : i32
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pipeline.latency.return %d : i32
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}
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pipeline.stage ^bb3
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^bb3(%s3_enable : i1):
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pipeline.stage ^bb4
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^bb4(%s4_enable : i1):
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%res = comb.add %out, %out2 : i32
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pipeline.return %out : i32
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}
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hw.output %out#0 : i32
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}
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// CHECK-LABEL: hw.module @testLatencyToLatency(
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// CHECK-SAME: in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[GO:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[RESET:.*]] : i1, out out : i32) {
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// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = pipeline.scheduled(%[[VAL_7:.*]] : i32 = %[[VAL_0]]) clock(%[[CLOCK]]) reset(%[[RESET]]) go(%[[GO]]) entryEn(%[[S0_VALID:.*]]) -> (out : i32) {
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// CHECK: %[[VAL_11:.*]] = hw.constant true
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// CHECK: %[[VAL_12:.*]] = pipeline.latency 2 -> (i32) {
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// CHECK: %[[VAL_13:.*]] = comb.add %[[VAL_7]], %[[VAL_7]] : i32
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// CHECK: pipeline.latency.return %[[VAL_13]] : i32
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// CHECK: }
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// CHECK: pipeline.stage ^bb1 pass(%[[VAL_14:.*]] : i32)
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// CHECK: ^bb1(%[[VAL_15:.*]]: i32, %[[VAL_16:.*]]: i1):
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// CHECK: pipeline.stage ^bb2 pass(%[[VAL_15]] : i32)
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// CHECK: ^bb2(%[[VAL_17:.*]]: i32, %[[VAL_18:.*]]: i1):
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// CHECK: %[[VAL_19:.*]] = pipeline.latency 2 -> (i32) {
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// CHECK: %[[VAL_20:.*]] = hw.constant 1 : i32
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// CHECK: %[[VAL_21:.*]] = comb.add %[[VAL_17]], %[[VAL_20]] : i32
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// CHECK: pipeline.latency.return %[[VAL_21]] : i32
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// CHECK: }
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// CHECK: pipeline.stage ^bb3 pass(%[[VAL_22:.*]] : i32)
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// CHECK: ^bb3(%[[VAL_23:.*]]: i32, %[[VAL_24:.*]]: i1):
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// CHECK: pipeline.stage ^bb4 pass(%[[VAL_23]] : i32)
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// CHECK: ^bb4(%[[VAL_25:.*]]: i32, %[[VAL_26:.*]]: i1):
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// CHECK: pipeline.return %[[VAL_25]] : i32
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// CHECK: }
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// CHECK: hw.output %[[VAL_27:.*]] : i32
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// CHECK: }
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hw.module @testLatencyToLatency(in %arg0: i32, in %arg1: i32, in %go: i1, in %clk : !seq.clock, in %rst: i1, out out: i32) {
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%0:2 = pipeline.scheduled(%a0 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%true = hw.constant true
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%1 = pipeline.latency 2 -> (i32) {
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%res = comb.add %a0, %a0 : i32
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pipeline.latency.return %res : i32
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}
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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%2 = pipeline.latency 2 -> (i32) {
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%c1_i32 = hw.constant 1 : i32
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%res2 = comb.add %1, %c1_i32 : i32
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pipeline.latency.return %res2 : i32
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}
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pipeline.stage ^bb3
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^bb3(%s3_enable : i1):
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pipeline.stage ^bb4
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^bb4(%s4_enable : i1):
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pipeline.return %2 : i32
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}
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hw.output %0#0 : i32
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}
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// CHECK-LABEL: hw.module @test_arbitrary_nesting(
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// CHECK-SAME: in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[GO:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[RESET:.*]] : i1, out out : i32) {
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// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]] = pipeline.scheduled(%[[VAL_7:.*]] : i32 = %[[VAL_0]]) clock(%[[CLOCK]]) reset(%[[RESET]]) go(%[[GO]]) entryEn(%[[S0_VALID:.*]]) -> (out : i32) {
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// CHECK: %[[VAL_11:.*]] = hw.constant true
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// CHECK: pipeline.stage ^bb1 regs("a0" = %[[VAL_7]] : i32)
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// CHECK: ^bb1(%[[VAL_12:.*]]: i32, %[[VAL_13:.*]]: i1):
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// CHECK: %[[VAL_14:.*]] = "foo.foo"(%[[VAL_12]]) : (i32) -> i32
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// CHECK: "foo.bar"() ({
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// CHECK: %[[VAL_15:.*]] = "foo.foo"(%[[VAL_12]]) : (i32) -> i32
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// CHECK: "foo.baz"() ({
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// CHECK: ^bb0(%[[VAL_16:.*]]: i32):
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// CHECK: "foo.foobar"(%[[VAL_14]], %[[VAL_15]], %[[VAL_16]]) : (i32, i32, i32) -> ()
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// CHECK: "foo.foobar"(%[[VAL_12]]) : (i32) -> ()
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// CHECK: }) : () -> ()
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// CHECK: }) : () -> ()
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// CHECK: pipeline.stage ^bb2 regs("a0" = %[[VAL_12]] : i32)
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// CHECK: ^bb2(%[[VAL_17:.*]]: i32, %[[VAL_18:.*]]: i1):
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// CHECK: pipeline.return %[[VAL_17]] : i32
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// CHECK: }
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// CHECK: hw.output %[[VAL_19:.*]] : i32
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// CHECK: }
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hw.module @test_arbitrary_nesting(in %arg0 : i32, in %arg1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%out:2 = pipeline.scheduled(%a0 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%true = hw.constant true
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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%foo = "foo.foo" (%a0) : (i32) -> (i32)
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"foo.bar" () ({
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^bb0:
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%foo2 = "foo.foo" (%a0) : (i32) -> (i32)
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"foo.baz" () ({
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^bb0(%innerArg0 : i32):
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// Reference all of the values defined above - none of these should
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// be registered.
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"foo.foobar" (%foo, %foo2, %innerArg0) : (i32, i32, i32) -> ()
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// Reference %a0 - this should be registered.
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"foo.foobar" (%a0) : (i32) -> ()
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}) : () -> ()
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}) : () -> ()
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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pipeline.return %a0 : i32
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}
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hw.output %out#0 : i32
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}
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// CHECK-LABEL: hw.module @testExtInput(
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// CHECK-SAME: in %[[VAL_0:.*]] : i32, in %[[VAL_1:.*]] : i32, in %[[GO:.*]] : i1, in %[[CLOCK:.*]] : !seq.clock, in %[[RESET:.*]] : i1, out out0 : i32, out out1 : i32) {
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// CHECK: %[[VAL_5:.*]], %[[VAL_6:.*]], %[[VAL_7:.*]] = pipeline.scheduled(%[[VAL_8:.*]] : i32 = %[[VAL_0]]) clock(%[[CLOCK]]) reset(%[[RESET]]) go(%[[GO]]) entryEn(%[[S0_VALID:.*]]) -> (out0 : i32, out1 : i32) {
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// CHECK: %[[VAL_13:.*]] = hw.constant true
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// CHECK: %[[VAL_14:.*]] = comb.add %[[VAL_8]], %[[VAL_1]] : i32
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// CHECK: pipeline.stage ^bb1 regs(%[[VAL_14]] : i32)
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// CHECK: ^bb1(%[[VAL_15:.*]]: i32, %[[VAL_16:.*]]: i1):
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// CHECK: pipeline.return %[[VAL_15]], %[[VAL_1]] : i32, i32
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// CHECK: }
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// CHECK: hw.output %[[VAL_17:.*]], %[[VAL_18:.*]] : i32, i32
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// CHECK: }
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hw.module @testExtInput(in %arg0 : i32, in %ext1 : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out0: i32, out out1: i32) {
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%out:3 = pipeline.scheduled(%a0 : i32 = %arg0) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out0: i32, out1: i32) {
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%true = hw.constant true
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%add0 = comb.add %a0, %ext1 : i32
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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pipeline.return %add0, %ext1 : i32, i32
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}
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hw.output %out#0, %out#1 : i32, i32
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}
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// CHECK-LABEL: hw.module @testNaming
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// CHECK-NEXT: %out, %done = pipeline.scheduled(%A : i32 = %myArg) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out : i32) {
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// CHECK-NEXT: %0 = pipeline.latency 2 -> (i32) {
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// CHECK-NEXT: %2 = comb.add %A, %A : i32
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// CHECK-NEXT: pipeline.latency.return %2 : i32
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// CHECK-NEXT: } {sv.namehint = "foo"}
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// CHECK-NEXT: pipeline.stage ^bb1 regs("A" = %A : i32) pass("foo" = %0 : i32)
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// CHECK-NEXT: ^bb1(%A_0: i32, %foo: i32, %s1_enable: i1): // pred: ^bb0
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// CHECK-NEXT: pipeline.stage ^bb2 regs("A" = %A_0 : i32) pass("foo" = %foo : i32)
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// CHECK-NEXT: ^bb2(%A_1: i32, %foo_2: i32, %s2_enable: i1): // pred: ^bb1
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// CHECK-NEXT: %1 = comb.add %A_1, %foo_2 {sv.namehint = "bar"} : i32
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// CHECK-NEXT: pipeline.stage ^bb3 regs("bar" = %1 : i32)
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// CHECK-NEXT: ^bb3(%bar: i32, %s3_enable: i1): // pred: ^bb2
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// CHECK-NEXT: pipeline.return %bar : i32
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// CHECK-NEXT: }
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// CHECK-NEXT: hw.output %out : i32
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// CHECK-NEXT: }
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hw.module @testNaming(in %myArg : i32, in %go : i1, in %clk : !seq.clock, in %rst : i1, out out: i32) {
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%out:2 = pipeline.scheduled(%A : i32 = %myArg) clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (out: i32) {
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%res = pipeline.latency 2 -> (i32) {
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%d = comb.add %A, %A : i32
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pipeline.latency.return %d : i32
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} {"sv.namehint" = "foo"}
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pipeline.stage ^bb1
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^bb1(%s1_enable : i1):
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pipeline.stage ^bb2
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^bb2(%s2_enable : i1):
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%0 = comb.add %A, %res {"sv.namehint" = "bar"} : i32
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pipeline.stage ^bb3
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^bb3(%s3_enable : i1):
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pipeline.return %0 : i32
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}
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hw.output %out#0 : i32
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}
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// CHECK-LABEL: hw.module @pipelineLatencyCrashRepro(
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// CHECK-SAME: in %[[CLOCK:.*]] : !seq.clock, in %[[VAL_1:.*]] : i1, in %[[GO:.*]] : i1) {
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// CHECK: %[[VAL_3:.*]], %[[VAL_4:.*]] = pipeline.scheduled() clock(%[[CLOCK]]) reset(%[[VAL_1]]) go(%[[GO]]) entryEn(%[[S0_VALID:.*]]) -> (pipeline_done : i128) {
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// CHECK: %[[VAL_8:.*]] = "dummy.op"() : () -> i128
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// CHECK: pipeline.stage ^bb1 regs(%[[VAL_8]] : i128)
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// CHECK: ^bb1(%[[VAL_9:.*]]: i128, %[[VAL_10:.*]]: i1):
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// CHECK: %[[VAL_11:.*]] = pipeline.latency 2 -> (i54) {
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// CHECK: %[[VAL_12:.*]] = "dummy.op"() : () -> i54
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// CHECK: pipeline.latency.return %[[VAL_12]] : i54
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// CHECK: }
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// CHECK: pipeline.stage ^bb2 regs(%[[VAL_9]] : i128) pass(%[[VAL_11]] : i54)
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// CHECK: ^bb2(%[[VAL_13:.*]]: i128, %[[VAL_14:.*]]: i54, %[[VAL_15:.*]]: i1):
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// CHECK: pipeline.stage ^bb3 regs(%[[VAL_13]] : i128) pass(%[[VAL_14]] : i54)
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// CHECK: ^bb3(%[[VAL_16:.*]]: i128, %[[VAL_17:.*]]: i54, %[[VAL_18:.*]]: i1):
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// CHECK: "dummy.op"(%[[VAL_17]]) : (i54) -> ()
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// CHECK: pipeline.stage ^bb4 regs(%[[VAL_16]] : i128)
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// CHECK: ^bb4(%[[VAL_19:.*]]: i128, %[[VAL_20:.*]]: i1):
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// CHECK: pipeline.return %[[VAL_19]] : i128
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// CHECK: }
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// CHECK: hw.output
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// CHECK: }
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// Tests an issue wherein the order of pass and reg operands was incorrect in
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// between the order that block arguments were added to a stage, and the order
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// that said block arguments were used to replace backedges within a block.
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hw.module @pipelineLatencyCrashRepro(in %clk : !seq.clock, in %rst: i1, in %go: i1) {
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%pipeline_done, %done = pipeline.scheduled() clock(%clk) reset(%rst) go(%go) entryEn(%s0_enable) -> (pipeline_done : i128) {
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%0 = "dummy.op"() : () -> i128
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pipeline.stage ^bb1
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^bb1(%s1_enable: i1): // pred: ^bb0
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%1 = pipeline.latency 2 -> (i54) {
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%2 = "dummy.op"() : () -> i54
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pipeline.latency.return %2 : i54
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}
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pipeline.stage ^bb2
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^bb2(%s2_enable: i1): // pred: ^bb1
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pipeline.stage ^bb3
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^bb3(%s3_enable: i1): // pred: ^bb2
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"dummy.op"(%1) : (i54) -> ()
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pipeline.stage ^bb4
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^bb4(%s4_enable: i1): // pred: ^bb3
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pipeline.return %0 : i128
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}
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hw.output
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|
}
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