mirror of https://github.com/llvm/circt.git
27 lines
725 B
MLIR
27 lines
725 B
MLIR
// RUN: circt-opt -om-freeze-paths --split-input-file --verify-diagnostics %s
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hw.hierpath private @nla [@Top::@sym]
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hw.module @Top() {
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// expected-note @below {{component here}}
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%wire = hw.wire %wire sym @sym : i8
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hw.output
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}
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om.class @OM(%basepath: !om.basepath) {
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// expected-error @below {{component does not have verilog name}}
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%path = om.path_create reference %basepath @nla
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om.class.fields
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}
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// -----
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hw.hierpath private @nla [@Top::@sym]
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hw.module @Top() {
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%wire = hw.wire %wire sym @sym {hw.verilogName = "wire"} : i8
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hw.output
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}
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om.class @OM(%basepath: !om.basepath) {
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// expected-error @below {{basepath must target an instance}}
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%path = om.basepath_create %basepath @nla
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om.class.fields
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}
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