mirror of https://github.com/llvm/circt.git
130 lines
5.5 KiB
MLIR
130 lines
5.5 KiB
MLIR
// RUN: circt-opt %s | circt-opt | FileCheck %s
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// Basic MLIR operation parser round-tripping
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firrtl.circuit "Basic" attributes {
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// CHECK: firrtl.specialization_disable = #firrtl<layerspecialization disable>
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firrtl.specialization_disable = #firrtl<layerspecialization disable>,
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// CHECK: firrtl.specialization_enable = #firrtl<layerspecialization enable>
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firrtl.specialization_enable = #firrtl<layerspecialization enable>
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} {
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firrtl.extmodule @Basic()
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// CHECK: firrtl.module @Top(in %arg0: !firrtl.uint<1>) attributes {portNames = [""]}
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firrtl.module @Top(in %arg0: !firrtl.uint<1>) attributes {portNames = [""]} {}
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// CHECK-LABEL: firrtl.module @Intrinsics
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firrtl.module @Intrinsics(in %ui : !firrtl.uint, in %clock: !firrtl.clock, in %ui1: !firrtl.uint<1>) {
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// CHECK-NEXT: firrtl.int.sizeof %ui : (!firrtl.uint) -> !firrtl.uint<32>
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%size = firrtl.int.sizeof %ui : (!firrtl.uint) -> !firrtl.uint<32>
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// CHECK-NEXT: firrtl.int.isX %ui : !firrtl.uint
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%isx = firrtl.int.isX %ui : !firrtl.uint
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// CHECK-NEXT: firrtl.int.plusargs.test "foo"
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// CHECK-NEXT: firrtl.int.plusargs.value "bar" : !firrtl.uint<5>
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%foo_found = firrtl.int.plusargs.test "foo"
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%bar_found, %bar_value = firrtl.int.plusargs.value "bar" : !firrtl.uint<5>
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// CHECK-NEXT: firrtl.int.clock_gate %clock, %ui1
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// CHECK-NEXT: firrtl.int.clock_gate %clock, %ui1, %ui1
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%cg0 = firrtl.int.clock_gate %clock, %ui1
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%cg1 = firrtl.int.clock_gate %clock, %ui1, %ui1
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// CHECK-NEXT: firrtl.int.generic "clock_gate" %clock, %ui1 : (!firrtl.clock, !firrtl.uint<1>)
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// CHECK-NEXT: firrtl.int.generic "noargs" : () -> !firrtl.uint<32>
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// CHECK-NEXT: firrtl.int.generic "params" <FORMAT: none = "foobar"> : () -> !firrtl.bundle<x: uint<1>>
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// CHECK-NEXT: firrtl.int.generic "params_and_operand" <X: i64 = 123> %ui1 : (!firrtl.uint<1>) -> !firrtl.clock
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// CHECK-NEXT: firrtl.int.generic "inputs" %clock, %ui1, %clock : (!firrtl.clock, !firrtl.uint<1>, !firrtl.clock) -> ()
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%cg2 = firrtl.int.generic "clock_gate" %clock, %ui1 : (!firrtl.clock, !firrtl.uint<1>) -> !firrtl.clock
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%noargs = firrtl.int.generic "noargs" : () -> !firrtl.uint<32>
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%p = firrtl.int.generic "params" <FORMAT: none = "foobar"> : () -> !firrtl.bundle<x: uint<1>>
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%po = firrtl.int.generic "params_and_operand" <X: i64 = 123> %ui1 : (!firrtl.uint<1>) -> !firrtl.clock
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firrtl.int.generic "inputs" %clock, %ui1, %clock : (!firrtl.clock, !firrtl.uint<1>, !firrtl.clock) -> ()
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}
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// CHECK-LABEL: firrtl.module @FPGAProbe
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firrtl.module @FPGAProbe(
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in %clock: !firrtl.clock,
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in %reset: !firrtl.uint<1>,
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in %in: !firrtl.uint<8>
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) {
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// CHECK: firrtl.int.fpga_probe %clock, %in : !firrtl.uint<8>
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firrtl.int.fpga_probe %clock, %in : !firrtl.uint<8>
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}
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// CHECK-LABEL: firrtl.option @Platform
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firrtl.option @Platform {
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// CHECK:firrtl.option_case @FPGA
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firrtl.option_case @FPGA
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// CHECK:firrtl.option_case @ASIC
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firrtl.option_case @ASIC
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}
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firrtl.module private @DefaultTarget(in %clock: !firrtl.clock) {}
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firrtl.module private @FPGATarget(in %clock: !firrtl.clock) {}
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firrtl.module private @ASICTarget(in %clock: !firrtl.clock) {}
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// CHECK-LABEL: firrtl.module @Foo
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firrtl.module @Foo(in %clock: !firrtl.clock) {
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// CHECK: %inst_clock = firrtl.instance_choice inst interesting_name @DefaultTarget alternatives @Platform
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// CHECK-SAME: { @FPGA -> @FPGATarget, @ASIC -> @ASICTarget } (in clock: !firrtl.clock)
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%inst_clock = firrtl.instance_choice inst interesting_name @DefaultTarget alternatives @Platform
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{ @FPGA -> @FPGATarget, @ASIC -> @ASICTarget } (in clock: !firrtl.clock)
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firrtl.matchingconnect %inst_clock, %clock : !firrtl.clock
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}
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// CHECK-LABEL: firrtl.layer @LayerA bind
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// CHECK-NEXT: firrtl.layer @LayerB inline
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firrtl.layer @LayerA bind {
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firrtl.layer @LayerB inline {}
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}
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// CHECK-LABEL: firrtl.module @Layers
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// CHECK-SAME: out %a: !firrtl.probe<uint<1>, @LayerA>
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// CHECK-SAME: out %b: !firrtl.rwprobe<uint<1>, @LayerA::@LayerB>
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firrtl.module @Layers(
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out %a: !firrtl.probe<uint<1>, @LayerA>,
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out %b: !firrtl.rwprobe<uint<1>, @LayerA::@LayerB>
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) {}
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// CHECK-LABEL: firrtl.module @LayersEnabled
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// CHECK-SAME: layers = [@LayerA]
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firrtl.module @LayersEnabled() attributes {layers = [@LayerA]} {
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}
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// CHECK-LABEL: firrtl.module @PropertyArithmetic
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firrtl.module @PropertyArithmetic() {
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%0 = firrtl.integer 1
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%1 = firrtl.integer 2
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// CHECK: firrtl.integer.add %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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%2 = firrtl.integer.add %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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// CHECK: firrtl.integer.mul %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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%3 = firrtl.integer.mul %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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// CHECK: firrtl.integer.shr %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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%4 = firrtl.integer.shr %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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// CHECK: firrtl.integer.shl %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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%5 = firrtl.integer.shl %0, %1 : (!firrtl.integer, !firrtl.integer) -> !firrtl.integer
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}
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// CHECK-LABEL: firrtl.module @PropertyListOps
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firrtl.module @PropertyListOps() {
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%0 = firrtl.integer 0
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%1 = firrtl.integer 1
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%2 = firrtl.integer 2
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// CHECK: [[L0:%.+]] = firrtl.list.create %0, %1
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%l0 = firrtl.list.create %0, %1 : !firrtl.list<integer>
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// CHECK: [[L1:%.+]] = firrtl.list.create %2
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%l1 = firrtl.list.create %2 : !firrtl.list<integer>
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// CHECK: firrtl.list.concat [[L0]], [[L1]] : !firrtl.list<integer>
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%concat = firrtl.list.concat %l0, %l1 : !firrtl.list<integer>
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}
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}
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