mirror of https://github.com/llvm/circt.git
140 lines
7.4 KiB
MLIR
140 lines
7.4 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl.module(merge-connections)))' %s | FileCheck %s --check-prefixes=CHECK,COMMON
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// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl.module(merge-connections{aggressive-merging=true})))' %s | FileCheck %s --check-prefixes=AGGRESSIVE,COMMON
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firrtl.circuit "Test" {
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// circuit Test :
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// module Test :
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// input a : {c: {clock: Clock, valid:UInt<1>}[2]}
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// output b : {c: {clock: Clock, valid:UInt<1>}[2]}
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// b <= a
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// COMMON-LABEL: firrtl.module @Test(
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// COMMON-NEXT: firrtl.matchingconnect %b, %a
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// COMMON-NEXT: }
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firrtl.module @Test(in %a: !firrtl.vector<bundle<clock: clock, valid: uint<1>>, 2>, out %b: !firrtl.vector<bundle<clock: clock, valid: uint<1>>, 2>) {
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%0 = firrtl.subindex %a[0] : !firrtl.vector<bundle<clock: clock, valid: uint<1>>, 2>
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%1 = firrtl.subindex %b[0] : !firrtl.vector<bundle<clock: clock, valid: uint<1>>, 2>
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%2 = firrtl.subfield %0[clock] : !firrtl.bundle<clock: clock, valid: uint<1>>
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%3 = firrtl.subfield %1[clock] : !firrtl.bundle<clock: clock, valid: uint<1>>
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firrtl.matchingconnect %3, %2 : !firrtl.clock
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%4 = firrtl.subfield %0[valid] : !firrtl.bundle<clock: clock, valid: uint<1>>
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%5 = firrtl.subfield %1[valid] : !firrtl.bundle<clock: clock, valid: uint<1>>
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firrtl.matchingconnect %5, %4 : !firrtl.uint<1>
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%6 = firrtl.subindex %a[1] : !firrtl.vector<bundle<clock: clock, valid: uint<1>>, 2>
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%7 = firrtl.subindex %b[1] : !firrtl.vector<bundle<clock: clock, valid: uint<1>>, 2>
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%8 = firrtl.subfield %6[clock] : !firrtl.bundle<clock: clock, valid: uint<1>>
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%9 = firrtl.subfield %7[clock] : !firrtl.bundle<clock: clock, valid: uint<1>>
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firrtl.matchingconnect %9, %8 : !firrtl.clock
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%10 = firrtl.subfield %6[valid] : !firrtl.bundle<clock: clock, valid: uint<1>>
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%11 = firrtl.subfield %7[valid] : !firrtl.bundle<clock: clock, valid: uint<1>>
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firrtl.matchingconnect %11, %10 : !firrtl.uint<1>
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}
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// circuit Bar :
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// module Bar :
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// output a : {b: UInt<1>, c:UInt<1>}
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// a.b <= UInt<1>(0)
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// a.c <= UInt<1>(1)
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// COMMON-LABEL: firrtl.module @Constant(
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// COMMON-NEXT: %0 = firrtl.aggregateconstant [0 : ui1, 1 : ui1]
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// COMMON-NEXT: firrtl.matchingconnect %a, %0
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// COMMON-NEXT: }
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firrtl.module @Constant(out %a: !firrtl.bundle<b: uint<1>, c: uint<1>>) {
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%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
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%c1_ui1 = firrtl.constant 1 : !firrtl.uint<1>
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%0 = firrtl.subfield %a[b] : !firrtl.bundle<b: uint<1>, c: uint<1>>
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%1 = firrtl.subfield %a[c] : !firrtl.bundle<b: uint<1>, c: uint<1>>
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firrtl.matchingconnect %0, %c0_ui1 : !firrtl.uint<1>
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firrtl.matchingconnect %1, %c1_ui1 : !firrtl.uint<1>
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}
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// AGGRESSIVE-LABEL: firrtl.module @ConcatToVector(
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// AGGRESSIVE-NEXT: %0 = firrtl.vectorcreate %s1, %s2 : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.vector<uint<1>, 2>
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// AGGRESSIVE-NEXT: firrtl.matchingconnect %sink, %0
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// AGGRESSIVE-NEXT: }
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// CHECK-LABEL: firrtl.module @ConcatToVector(
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// CHECK-NEXT: %0 = firrtl.subindex %sink[1]
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// CHECK-NEXT: %1 = firrtl.subindex %sink[0]
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// CHECK-NEXT: firrtl.matchingconnect %1, %s1
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// CHECK-NEXT: firrtl.matchingconnect %0, %s2
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// CHECK-NEXT: }
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firrtl.module @ConcatToVector(in %s1: !firrtl.uint<1>, in %s2: !firrtl.uint<1>, out %sink: !firrtl.vector<uint<1>, 2>) {
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%0 = firrtl.subindex %sink[1] : !firrtl.vector<uint<1>, 2>
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%1 = firrtl.subindex %sink[0] : !firrtl.vector<uint<1>, 2>
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firrtl.matchingconnect %1, %s1 : !firrtl.uint<1>
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firrtl.matchingconnect %0, %s2 : !firrtl.uint<1>
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}
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// Check that we don't use %s1 as a source value.
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// AGGRESSIVE-LABEL: firrtl.module @FailedToUseAggregate(
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// AGGRESSIVE-NEXT: %0 = firrtl.subindex %s1[0]
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// AGGRESSIVE-NEXT: %1 = firrtl.vectorcreate %0, %s2
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// AGGRESSIVE-NEXT: firrtl.matchingconnect %sink, %1
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// AGGRESSIVE-NEXT: }
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// CHECK-LABEL: firrtl.module @FailedToUseAggregate(
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// CHECK-NEXT: %0 = firrtl.subindex %sink[1]
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// CHECK-NEXT: %1 = firrtl.subindex %s1[0]
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// CHECK-NEXT: %2 = firrtl.subindex %sink[0]
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// CHECK-NEXT: firrtl.matchingconnect %2, %1
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// CHECK-NEXT: firrtl.matchingconnect %0, %s2
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// CHECK-NEXT: }
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firrtl.module @FailedToUseAggregate(in %s1: !firrtl.vector<uint<1>, 2>, in %s2: !firrtl.uint<1>, out %sink: !firrtl.vector<uint<1>, 2>) {
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%0 = firrtl.subindex %sink[1] : !firrtl.vector<uint<1>, 2>
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%1 = firrtl.subindex %s1[0] : !firrtl.vector<uint<1>, 2>
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%2 = firrtl.subindex %sink[0] : !firrtl.vector<uint<1>, 2>
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firrtl.matchingconnect %2, %1 : !firrtl.uint<1>
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firrtl.matchingconnect %0, %s2 : !firrtl.uint<1>
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}
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// No merging with non-passive type.
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// COMMON-LABEL: firrtl.module private @DUT
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// COMMON-NEXT: %p = firrtl.wire
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// COMMON-NEXT: %0 = firrtl.subfield
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// COMMON-NEXT: firrtl.matchingconnect %0, %x_a
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// COMMON-NEXT: %1 = firrtl.subfield
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// COMMON-NEXT: firrtl.matchingconnect %x_b, %1
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// COMMON-NEXT: firrtl.matchingconnect %y_a, %0
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// COMMON-NEXT: firrtl.matchingconnect %1, %y_b
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// COMMON-NEXT: }
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firrtl.module private @DUT(in %x_a: !firrtl.uint<2>,
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out %x_b: !firrtl.uint<2>,
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out %y_a: !firrtl.uint<2>,
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in %y_b: !firrtl.uint<2>) {
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%p = firrtl.wire : !firrtl.bundle<a: uint<2>, b flip: uint<2>>
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%0 = firrtl.subfield %p[a] : !firrtl.bundle<a: uint<2>, b flip: uint<2>>
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firrtl.matchingconnect %0, %x_a : !firrtl.uint<2>
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%1 = firrtl.subfield %p[b] : !firrtl.bundle<a: uint<2>, b flip: uint<2>>
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firrtl.matchingconnect %x_b, %1 : !firrtl.uint<2>
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firrtl.matchingconnect %y_a, %0 : !firrtl.uint<2>
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firrtl.matchingconnect %1, %y_b : !firrtl.uint<2>
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}
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// Don't create aggregateconstant of non-passive. #6259.
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// COMMON-LABEL: @Issue6259
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// COMMON-NOT: aggregateconstant
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// COMMON: }
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firrtl.module private @Issue6259(out %a: !firrtl.rwprobe<bundle<a: uint<1>, b: uint<2>>>) {
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%c0_ui2 = firrtl.constant 0 : !firrtl.uint<2>
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%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
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%w, %w_ref = firrtl.wire forceable {annotations = [{class = "firrtl.transforms.DontTouchAnnotation"}]} : !firrtl.bundle<a: uint<1>, b flip: uint<2>>, !firrtl.rwprobe<bundle<a: uint<1>, b: uint<2>>>
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%0 = firrtl.subfield %w[b] : !firrtl.bundle<a: uint<1>, b flip: uint<2>>
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%1 = firrtl.subfield %w[a] : !firrtl.bundle<a: uint<1>, b flip: uint<2>>
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firrtl.matchingconnect %1, %c0_ui1 : !firrtl.uint<1>
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firrtl.matchingconnect %0, %c0_ui2 : !firrtl.uint<2>
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firrtl.ref.define %a, %w_ref : !firrtl.rwprobe<bundle<a: uint<1>, b: uint<2>>>
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}
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// COMMON-LABEL: @Alias
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firrtl.module @Alias(in %i: !firrtl.alias<MyBundle, bundle<f: uint<1>, b: uint<1>>>, out %o: !firrtl.alias<MyBundle, bundle<f: uint<1>, b: uint<1>>>) {
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// CHECK-NEXT: firrtl.matchingconnect %o, %i
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%0 = firrtl.subfield %i[f] : !firrtl.alias<MyBundle, bundle<f: uint<1>, b: uint<1>>>
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%1 = firrtl.subfield %o[f] : !firrtl.alias<MyBundle, bundle<f: uint<1>, b: uint<1>>>
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firrtl.matchingconnect %1, %0 : !firrtl.uint<1>
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%2 = firrtl.subfield %i[b] : !firrtl.alias<MyBundle, bundle<f: uint<1>, b: uint<1>>>
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%3 = firrtl.subfield %o[b] : !firrtl.alias<MyBundle, bundle<f: uint<1>, b: uint<1>>>
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firrtl.matchingconnect %3, %2 : !firrtl.uint<1>
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}
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}
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