mirror of https://github.com/llvm/circt.git
283 lines
18 KiB
MLIR
283 lines
18 KiB
MLIR
// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-mem-to-reg-of-vec))' %s | FileCheck %s
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firrtl.circuit "Mem" attributes {annotations = [{class = "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"}]}{
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firrtl.module public @Mem(out %d : !firrtl.probe<vector<uint<8>, 8>>, out %d2 : !firrtl.probe<vector<uint<8>, 8>>) attributes {annotations = [
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{class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}
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]} {
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%dbg, %mem_read, %mem_write, %debug = firrtl.mem Undefined {
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depth = 8 : i64,
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name = "mem",
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portNames = ["dbg", "read", "write", "debug"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.probe<vector<uint<8>, 8>>, !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data flip: uint<8>>,
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!firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: uint<8>, mask: uint<1>>,
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!firrtl.probe<vector<uint<8>, 8>>
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firrtl.ref.define %d, %debug : !firrtl.probe<vector<uint<8>, 8>>
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firrtl.ref.define %d2, %dbg : !firrtl.probe<vector<uint<8>, 8>>
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}
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// CHECK-LABEL: firrtl.circuit "Mem" {
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// CHECK: firrtl.module public @Mem(
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// CHECK: %mem_read = firrtl.wire : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data flip: uint<8>>
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// CHECK: %[[v0:.+]] = firrtl.subfield %mem_read[addr]
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// CHECK: %[[v1:.+]] = firrtl.subfield %mem_read[en]
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// CHECK: %[[v2:.+]] = firrtl.subfield %mem_read[clk]
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// CHECK: %[[v3:.+]] = firrtl.subfield %mem_read[data]
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// CHECK: %mem = firrtl.reg %[[v6:.+]] : !firrtl.clock, !firrtl.vector<uint<8>, 8>
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// CHECK: %[[v23:.+]] = firrtl.subaccess %mem[%[[v4:.+]]]
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// CHECK: %invalid_ui8 = firrtl.invalidvalue : !firrtl.uint<8>
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// CHECK: firrtl.matchingconnect %[[v3]], %invalid_ui8 : !firrtl.uint<8>
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// CHECK: firrtl.when %[[v1]] : !firrtl.uint<1> {
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// CHECK: firrtl.matchingconnect %[[v3]], %[[v23]]
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// CHECK: }
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// CHECK: %mem_write = firrtl.wire : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: uint<8>, mask: uint<1>>
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// CHECK: %[[v5:.+]] = firrtl.subfield %mem_write[addr]
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// CHECK: %[[v6:.+]] = firrtl.subfield %mem_write[en]
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// CHECK: %[[v7:.+]] = firrtl.subfield %mem_write[clk]
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// CHECK: %[[v8:.+]] = firrtl.subfield %mem_write[data]
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// CHECK: %[[v9:.+]] = firrtl.subfield %mem_write[mask]
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// CHECK: %[[v10:.+]] = firrtl.subaccess %mem[%[[v5]]]
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// CHECK: firrtl.when %[[v6]] : !firrtl.uint<1> {
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// CHECK: firrtl.when %[[v9]] : !firrtl.uint<1> {
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// CHECK: firrtl.matchingconnect %[[v10]], %[[v8]] : !firrtl.uint<8>
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// CHECK: }
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// CHECK: }
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// CHECK: %11 = firrtl.ref.send %mem : !firrtl.vector<uint<8>, 8>
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// CHECK: %12 = firrtl.ref.send %mem : !firrtl.vector<uint<8>, 8>
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// CHECK: firrtl.ref.define %d, %12 : !firrtl.probe<vector<uint<8>, 8>>
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// CHECK: firrtl.ref.define %d2, %11 : !firrtl.probe<vector<uint<8>, 8>>
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}
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firrtl.circuit "Mem_Ignore" {
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firrtl.module public @Mem_Ignore() attributes {annotations = [
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{class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}
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]} {
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%mem_read, %mem_write = firrtl.mem Undefined {
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depth = 8 : i64,
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name = "mem",
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portNames = ["read", "write"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data flip: uint<8>>,
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!firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: uint<8>, mask: uint<1>>
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// CHECK: %mem_read, %mem_write = firrtl.mem Undefined
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// CHECK-SAME: {depth = 8 : i64, name = "mem", portNames = ["read", "write"], readLatency = 0 : i32, writeLatency = 1 : i32}
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// CHECK-SAME: : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data flip: uint<8>>,
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// CHECK-SAME: !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: uint<8>, mask: uint<1>>
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}
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}
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firrtl.circuit "GCTModule" attributes {annotations = [
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{class = "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"}
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]} {
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firrtl.module public @GCTModule() attributes {annotations = [
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{class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}
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]} {
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%rf_read, %rf_write = firrtl.mem Undefined {
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annotations = [
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{circt.fieldID = 1 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 1 : i64, type = "source"},
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{circt.fieldID = 1 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 2 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 2 : i64, type = "source"},
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{circt.fieldID = 2 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 3 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 3 : i64, type = "source"},
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{circt.fieldID = 3 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 4 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 4 : i64, type = "source"},
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{circt.fieldID = 4 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 5 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 5 : i64, type = "source"},
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{circt.fieldID = 5 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 6 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 6 : i64, type = "source"},
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{circt.fieldID = 6 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 7 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 7 : i64, type = "source"},
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{circt.fieldID = 7 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 8 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 8 : i64, type = "source"},
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{circt.fieldID = 8 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 1 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 2 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 3 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 4 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 5 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 6 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 7 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 8 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 1 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 2 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 3 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 4 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 5 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 6 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 7 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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{circt.fieldID = 8 : i64, class = "firrtl.transforms.DontTouchAnnotation"}
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],
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depth = 8 : i64,
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name = "rf",
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portNames = ["read",
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"write"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data flip: uint<8>>,
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!firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: uint<8>, mask: uint<1>>
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// CHECK-LABEL: firrtl.module public @GCTModule()
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// CHECK: %rf = firrtl.reg %2
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// CHECK-SAME: {circt.fieldID = 1 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 1 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 1 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 2 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 2 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 2 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 3 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 3 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 3 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 4 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 4 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 4 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 5 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 5 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 5 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 6 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 6 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 6 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 7 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 7 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 7 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 8 : i64, class = "sifive.enterprise.grandcentral.ReferenceDataTapKey", id = 0 : i64, portID = 8 : i64, type = "source"},
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// CHECK-SAME: {circt.fieldID = 8 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 1 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 2 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 3 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 4 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 5 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 6 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 7 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 8 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 1 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 2 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 3 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 4 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 5 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 6 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 7 : i64, class = "firrtl.transforms.DontTouchAnnotation"},
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// CHECK-SAME: {circt.fieldID = 8 : i64, class = "firrtl.transforms.DontTouchAnnotation"}]} : !firrtl.clock, !firrtl.vector<uint<8>, 8>
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}
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}
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firrtl.circuit "WriteMask" attributes {annotations = [
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{class = "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"}
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]} {
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firrtl.module public @WriteMask() attributes {annotations = [
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{class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}
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]} {
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%mem_read, %mem_write = firrtl.mem Undefined {
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depth = 8 : i64,
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name = "mem",
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portNames = ["read", "write"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data flip: vector<uint<8>, 2>>,
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!firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: vector<uint<8>, 2>, mask: vector<uint<1>, 2>>
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// CHECK-LABEL: firrtl.module public @WriteMask()
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// CHECK: %mem = firrtl.reg %2 : !firrtl.clock, !firrtl.vector<vector<uint<8>, 2>, 8>
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// CHECK: %mem_write = firrtl.wire : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: vector<uint<8>, 2>, mask: vector<uint<1>, 2>>
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// CHECK: %[[v5:.+]] = firrtl.subfield %mem_write[addr]
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// CHECK: %[[v6:.+]] = firrtl.subfield %mem_write[en]
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// CHECK: %[[v7:.+]] = firrtl.subfield %mem_write[clk]
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// CHECK: %[[v8:.+]] = firrtl.subfield %mem_write[data]
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// CHECK: %[[v9:.+]] = firrtl.subfield %mem_write[mask]
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// CHECK: %[[v10:.+]] = firrtl.subaccess %mem[%5] : !firrtl.vector<vector<uint<8>, 2>, 8>, !firrtl.uint<3>
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// CHECK: %[[v11:.+]] = firrtl.subindex
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// CHECK: %[[v12:.+]] = firrtl.subindex
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// CHECK: %[[v13:.+]] = firrtl.subindex
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// CHECK: %[[v14:.+]] = firrtl.subindex
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// CHECK: %[[v15:.+]] = firrtl.subindex
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// CHECK: %[[v16:.+]] = firrtl.subindex
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// CHECK: firrtl.when %[[v6]] : !firrtl.uint<1> {
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// CHECK: firrtl.when %[[v13]] : !firrtl.uint<1> {
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// CHECK: firrtl.matchingconnect %[[v11]], %[[v12]] : !firrtl.uint<8>
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// CHECK: }
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// CHECK: firrtl.when %[[v16]] : !firrtl.uint<1> {
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// CHECK: firrtl.matchingconnect %[[v14]], %[[v15]] : !firrtl.uint<8>
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// CHECK: }
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%mem_read1, %mem_write1 = firrtl.mem Undefined {
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annotations = [
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{class = "sifive.enterprise.firrtl.ExcludeMemFromMemToRegOfVec"}
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],
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depth = 8 : i64,
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name = "mem",
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portNames = ["read", "write"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data flip: vector<uint<8>, 2>>,
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!firrtl.bundle<addr: uint<3>, en: uint<1>, clk: clock, data: vector<uint<8>, 2>, mask: vector<uint<1>, 2>>
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// CHECK: %mem_read_0, %mem_write_1 = firrtl.mem Undefined {depth = 8 :
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}
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}
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firrtl.circuit "MemTap" attributes {annotations = [
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{class = "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"}
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]} {
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firrtl.module public @MemTap() attributes {annotations = [
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{class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}
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]} {
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%rf_MPORT, %rf_io_rdata_0_MPORT, %rf_io_rdata_1_MPORT = firrtl.mem sym @rf Undefined {
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annotations = [
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{class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64}
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],
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depth = 4 : i64,
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name = "rf",
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portNames = ["MPORT", "io_rdata_0_MPORT", "io_rdata_1_MPORT"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data: uint<32>, mask: uint<1>>,
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!firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data flip: uint<32>>,
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!firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data flip: uint<32>>
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// CHECK-LABEL: firrtl.module public @MemTap()
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// CHECK: %rf = firrtl.reg sym @rf %2
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// CHECK-SAME: [{circt.fieldID = 1 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 0 : i64}
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// CHECK-SAME: {circt.fieldID = 2 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 1 : i64},
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// CHECK-SAME: {circt.fieldID = 3 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 2 : i64},
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// CHECK-SAME: {circt.fieldID = 4 : i64, class = "sifive.enterprise.grandcentral.MemTapAnnotation.source", id = 11 : i64, portID = 3 : i64}]}
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// CHECK-SAME: : !firrtl.clock, !firrtl.vector<uint<32>, 4>
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}
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}
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// Test the behavior of non-local annotations using either the old or new
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// format work correctly.
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//
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// CHECK-LABEL: "NLA"
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firrtl.circuit "NLA" attributes {annotations = [
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{class = "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$"}
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]} {
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// The hierachical paths are unchanged.
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// CHECK: hw.hierpath private @path_old [@NLA::@foo, @Foo::@old]
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// CHECK-NEXT: hw.hierpath private @path_new [@NLA::@foo, @Foo]
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hw.hierpath private @path_old [@NLA::@foo, @Foo::@old]
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hw.hierpath private @path_new [@NLA::@foo, @Foo]
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firrtl.module private @Foo() {
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// CHECK: %old = firrtl.reg sym @old
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// CHECK-SAME: {circt.nonlocal = @path, class = "oldNLA"}
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%old_r = firrtl.mem sym @old Undefined {
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annotations = [
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{circt.nonlocal = @path, class = "oldNLA"}
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],
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depth = 4 : i64,
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name = "old",
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portNames = ["r"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data flip: uint<32>>
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// CHECK: %new = firrtl.reg
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// CHECK-NOT: sym
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// CHECK-SAME: {circt.nonlocal = @path, class = "newNLA"}
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%new_r = firrtl.mem Undefined {
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annotations = [
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{circt.nonlocal = @path, class = "newNLA"}
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],
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depth = 4 : i64,
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name = "new",
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portNames = ["r"],
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readLatency = 0 : i32,
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writeLatency = 1 : i32
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} : !firrtl.bundle<addr: uint<2>, en: uint<1>, clk: clock, data flip: uint<32>>
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}
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firrtl.module public @NLA() attributes {annotations = [
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{class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}
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]} {
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firrtl.instance foo sym @foo @Foo()
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|
}
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|
}
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