mirror of https://github.com/llvm/circt.git
70 lines
2.6 KiB
MLIR
70 lines
2.6 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl.module(firrtl-materialize-debug-info)))' %s | FileCheck %s
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firrtl.circuit "Ports" {
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// CHECK-LABEL: firrtl.module @Ports
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firrtl.module @Ports(
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in %inA: !firrtl.uint<42>,
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in %inB: !firrtl.bundle<a: sint<19>, b: clock>,
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in %inC: !firrtl.vector<asyncreset, 2>,
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in %inD: !firrtl.bundle<clocks: vector<clock, 4>>,
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out %outA: !firrtl.uint<42>
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) {
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// CHECK-NEXT: dbg.variable "inA", %inA
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// CHECK-NEXT: [[TMP0:%.+]] = firrtl.subfield %inB[a]
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// CHECK-NEXT: [[TMP1:%.+]] = firrtl.subfield %inB[b]
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// CHECK-NEXT: [[TMP:%.+]] = dbg.struct {"a": [[TMP0]], "b": [[TMP1]]}
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// CHECK-NEXT: dbg.variable "inB", [[TMP]]
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// CHECK-NEXT: [[TMP0:%.+]] = firrtl.subindex %inC[0]
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// CHECK-NEXT: [[TMP1:%.+]] = firrtl.subindex %inC[1]
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// CHECK-NEXT: [[TMP:%.+]] = dbg.array [[[TMP0]], [[TMP1]]]
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// CHECK-NEXT: dbg.variable "inC", [[TMP]]
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// CHECK-NEXT: [[TMP1:%.+]] = firrtl.subfield %inD[clocks]
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// CHECK-NEXT: [[TMP2:%.+]] = firrtl.subindex [[TMP1]][0]
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// CHECK-NEXT: [[TMP3:%.+]] = firrtl.subindex [[TMP1]][1]
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// CHECK-NEXT: [[TMP4:%.+]] = firrtl.subindex [[TMP1]][2]
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// CHECK-NEXT: [[TMP5:%.+]] = firrtl.subindex [[TMP1]][3]
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// CHECK-NEXT: [[TMP6:%.+]] = dbg.array [[[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]]]
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// CHECK-NEXT: [[TMP7:%.+]] = dbg.struct {"clocks": [[TMP6]]}
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// CHECK-NEXT: dbg.variable "inD", [[TMP7]]
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// CHECK-NEXT: dbg.variable "outA", %outA
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// CHECK-NEXT: firrtl.matchingconnect
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firrtl.matchingconnect %outA, %inA : !firrtl.uint<42>
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}
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// CHECK-LABEL: firrtl.module @Decls
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firrtl.module @Decls() {
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// CHECK-NEXT: firrtl.constant
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// CHECK-NEXT: firrtl.constant
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// CHECK-NEXT: firrtl.specialconstant
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%c0_ui1 = firrtl.constant 0 : !firrtl.uint<1>
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%c0_ui17 = firrtl.constant 0 : !firrtl.uint<17>
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%c0_clock = firrtl.specialconstant 0 : !firrtl.clock
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// CHECK-NEXT: firrtl.wire
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// CHECK-NEXT: dbg.variable "someWire", %someWire
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%someWire = firrtl.wire : !firrtl.uint<17>
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// CHECK-NEXT: firrtl.node
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// CHECK-NEXT: dbg.variable "someNode", %someNode
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%someNode = firrtl.node %c0_ui17 : !firrtl.uint<17>
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// CHECK-NEXT: firrtl.reg
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// CHECK-NEXT: dbg.variable "someReg1", %someReg1
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%someReg1 = firrtl.reg %c0_clock : !firrtl.clock, !firrtl.uint<17>
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// CHECK-NEXT: firrtl.regreset
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// CHECK-NEXT: dbg.variable "someReg2", %someReg2
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%someReg2 = firrtl.regreset %c0_clock, %c0_ui1, %c0_ui17 : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<17>, !firrtl.uint<17>
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// CHECK-NEXT: firrtl.matchingconnect
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firrtl.matchingconnect %someWire, %c0_ui17 : !firrtl.uint<17>
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}
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}
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