mirror of https://github.com/llvm/circt.git
103 lines
4.8 KiB
MLIR
103 lines
4.8 KiB
MLIR
// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-signatures))' %s | FileCheck --check-prefixes=CHECK %s
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// RUN: circt-opt -pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-signatures))' --mlir-print-debuginfo %s | FileCheck --check-prefixes=CHECK-LOC %s
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firrtl.circuit "Prop" {
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// CHECK-LABEL @Prop(out %y: !firrtl.string)
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firrtl.module @Prop(out %y: !firrtl.string) attributes {convention = #firrtl<convention scalarized>} {
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%0 = firrtl.string "test"
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// CHECK: firrtl.propassign
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firrtl.propassign %y, %0 : !firrtl.string
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}
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firrtl.module private @emptyVec(in %vi : !firrtl.vector<uint<4>, 0>, out %vo : !firrtl.vector<uint<4>, 0>) attributes {convention = #firrtl<convention scalarized>} {
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firrtl.matchingconnect %vo, %vi : !firrtl.vector<uint<4>, 0>
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}
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// CHECK-LABEL: @Annos
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// CHECK-SAME: in %x: !firrtl.uint<1> [{class = "circt.test", pin = "pin0"}],
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// CHECK-SAME: in %y_a: !firrtl.uint<1> [{class = "circt.test", pin = "pin1"}],
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// CHECK-SAME: in %y_b: !firrtl.uint<2> [{class = "circt.test", pin = "pin2"}])
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firrtl.module private @Annos(
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in %x: !firrtl.uint<1> [{circt.fieldID = 0 : i64, class = "circt.test", pin = "pin0"}],
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in %y: !firrtl.bundle<a: uint<1>, b: uint<2>> [{circt.fieldID = 2 : i64, class = "circt.test", pin = "pin2"}, {circt.fieldID = 1 : i64, class = "circt.test", pin = "pin1"}]
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) attributes {convention = #firrtl<convention scalarized>} {
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}
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// CHECK-LABEL: @AnalogBlackBox
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firrtl.extmodule private @AnalogBlackBox<index: ui32 = 0>(out bus: !firrtl.analog<32>) attributes {convention = #firrtl<convention scalarized>, defname = "AnalogBlackBox"}
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firrtl.module @AnalogBlackBoxModule(out %io: !firrtl.bundle<bus: analog<32>>) attributes {convention = #firrtl<convention scalarized>} {
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// CHECK: %io = firrtl.wire interesting_name : !firrtl.bundle<bus: analog<32>>
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// CHECK: %0 = firrtl.subfield %io[bus] : !firrtl.bundle<bus: analog<32>>
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// CHECK: firrtl.attach %0, %io_bus : !firrtl.analog<32>, !firrtl.analog<32>
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%0 = firrtl.subfield %io[bus] : !firrtl.bundle<bus: analog<32>>
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%impl_bus = firrtl.instance impl interesting_name @AnalogBlackBox(out bus: !firrtl.analog<32>)
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firrtl.attach %0, %impl_bus : !firrtl.analog<32>, !firrtl.analog<32>
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}
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// CHECK-LABEL: firrtl.module private @Bar
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firrtl.module private @Bar(out %in1: !firrtl.bundle<a flip: uint<1>, b flip: uint<1>>, in %in2: !firrtl.bundle<c: uint<1>>, in %out: !firrtl.bundle<d flip: uint<1>, e flip: uint<1>>) attributes {convention = #firrtl<convention scalarized>} {
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// CHECK-NEXT: %in1 = firrtl.wire
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// CHECK-NEXT: %in2 = firrtl.wire
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// CHECK-NEXT: %out = firrtl.wire
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}
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// CHECK-LABEL: firrtl.module private @Foo
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firrtl.module private @Foo() attributes {convention = #firrtl<convention scalarized>} {
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%bar_in1, %bar_in2, %bar_out = firrtl.instance bar interesting_name @Bar(out in1: !firrtl.bundle<a flip: uint<1>, b flip: uint<1>>, in in2: !firrtl.bundle<c: uint<1>>, in out: !firrtl.bundle<d flip: uint<1>, e flip: uint<1>>)
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// CHECK: %bar.in1 = firrtl.wire
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// CHECK: %bar.in2 = firrtl.wire
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// CHECK: %bar.out = firrtl.wire
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}
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}
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// Instances should preserve their location.
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// See https://github.com/llvm/circt/issues/6535
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firrtl.circuit "PreserveLocation" {
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firrtl.extmodule @Foo()
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// CHECK-LOC-LABEL: firrtl.module @PreserveLocation
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firrtl.module @PreserveLocation() {
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// CHECK-LOC: firrtl.instance foo @Foo() loc([[LOC:#.+]])
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firrtl.instance foo @Foo() loc(#instLoc)
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} loc(#moduleLoc)
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}
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// CHECK-LOC: [[LOC]] = loc("someLoc":9001:1)
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#moduleLoc = loc("wrongLoc":42:1)
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#instLoc = loc("someLoc":9001:1)
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// Internal paths should be expanded
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firrtl.circuit "InternalPaths" {
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// CHECK: firrtl.extmodule private @BlackBox
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// CHECK-SAME: out bundle_a: !firrtl.uint<32>, out bundle_b: !firrtl.uint<23>
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// CHECK-SAME: out array_0: !firrtl.uint<1>, out array_1: !firrtl.uint<1>
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// CHECK-SAME: out probe: !firrtl.probe<uint<32>>
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// CHECK-SAME: internalPaths = [
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// CHECK-SAME: #firrtl.internalpath
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// CHECK-SAME: #firrtl.internalpath
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// CHECK-SAME: #firrtl.internalpath
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// CHECK-SAME: #firrtl.internalpath
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// CHECK-SAME: #firrtl.internalpath<"some_probe">
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// CHECK-SAME: ]
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firrtl.extmodule private @BlackBox(
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out bundle : !firrtl.bundle<a: uint<32>, b: uint<23>>,
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out array : !firrtl.vector<uint<1>, 2>,
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out probe : !firrtl.probe<uint<32>>
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) attributes {
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convention = #firrtl<convention scalarized>,
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internalPaths = [
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#firrtl.internalpath,
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#firrtl.internalpath,
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#firrtl.internalpath<"some_probe">
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]
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}
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// CHECK-LABEL: @InternalPaths
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firrtl.module @InternalPaths() {
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%bundle, %array, %probe = firrtl.instance blackbox @BlackBox(
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out bundle : !firrtl.bundle<a: uint<32>, b: uint<23>>,
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out array : !firrtl.vector<uint<1>, 2>,
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out probe : !firrtl.probe<uint<32>>
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)
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}
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}
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