mirror of https://github.com/llvm/circt.git
58 lines
2.4 KiB
MLIR
58 lines
2.4 KiB
MLIR
// RUN: circt-opt --pass-pipeline="builtin.module(firrtl.circuit(firrtl-lower-open-aggs))" %s --split-input-file --verify-diagnostics
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firrtl.circuit "Symbol" {
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// expected-error @below {{inner symbol "bad" mapped to non-HW type}}
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firrtl.module @Symbol(out %r : !firrtl.openbundle<p: probe<uint<1>>> sym @bad) {
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%zero = firrtl.constant 0 : !firrtl.uint<1>
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%ref = firrtl.ref.send %zero : !firrtl.uint<1>
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%r_p = firrtl.opensubfield %r[p] : !firrtl.openbundle<p: probe<uint<1>>>
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firrtl.ref.define %r_p, %ref : !firrtl.probe<uint<1>>
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}
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}
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// -----
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firrtl.circuit "SymbolOnField" {
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// expected-error @below {{inner symbol "bad" mapped to non-HW type}}
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firrtl.extmodule @SymbolOnField(out r : !firrtl.openbundle<p: probe<uint<1>>, x: uint<1>> sym [<@bad,1,public>])
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}
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// -----
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firrtl.circuit "Annotation" {
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// expected-error @below {{annotations found on aggregate with no HW}}
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firrtl.module @Annotation(out %r : !firrtl.openbundle<p: probe<uint<1>>>) attributes {portAnnotations = [[{class = "circt.test"}]]} {
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%zero = firrtl.constant 0 : !firrtl.uint<1>
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%ref = firrtl.ref.send %zero : !firrtl.uint<1>
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%r_p = firrtl.opensubfield %r[p] : !firrtl.openbundle<p: probe<uint<1>>>
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firrtl.ref.define %r_p, %ref : !firrtl.probe<uint<1>>
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}
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}
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// -----
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// Open aggregates are expected to be removed before annotations,
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// but check this is detected and an appropriate diagnostic is presented.
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firrtl.circuit "MixedAnnotation" {
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// expected-error @below {{annotations on open aggregates not handled yet}}
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firrtl.module @MixedAnnotation(out %r : !firrtl.openbundle<a: uint<1>, p: probe<uint<1>>>) attributes {portAnnotations = [[{class = "circt.test"}]]} {
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%zero = firrtl.constant 0 : !firrtl.uint<1>
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%ref = firrtl.ref.send %zero : !firrtl.uint<1>
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%r_p = firrtl.opensubfield %r[p] : !firrtl.openbundle<a: uint<1>, p: probe<uint<1>>>
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firrtl.ref.define %r_p, %ref : !firrtl.probe<uint<1>>
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%r_a = firrtl.opensubfield %r[a] : !firrtl.openbundle<a: uint<1>, p: probe<uint<1>>>
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firrtl.matchingconnect %r_a, %zero : !firrtl.uint<1>
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}
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}
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// -----
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// As above, check that no annotations are seen. This should never occur in
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// firtool.
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firrtl.circuit "WireAnnotations" {
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firrtl.module @WireAnnotations() {
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// expected-error @below {{annotations on open aggregates not handled yet}}
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%a = firrtl.wire {annotations = [{class = "circt.test"}]} : !firrtl.openbundle<b: string, c: uint<1>>
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}
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}
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