mirror of https://github.com/llvm/circt.git
168 lines
11 KiB
MLIR
168 lines
11 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl.module(firrtl-lower-intrinsics)))' %s | FileCheck %s --check-prefixes=CHECK --implicit-check-not firrtl.int.generic
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// CHECK-LABEL: "Foo"
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firrtl.circuit "Foo" {
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// CHECK-LABEL: @Foo
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firrtl.module @Foo(in %clk : !firrtl.clock, out %s : !firrtl.uint<32>, out %io1 : !firrtl.uint<1>, out %io2 : !firrtl.uint<1>, out %io3 : !firrtl.uint<1>, out %io4 : !firrtl.uint<5>) {
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// CHECK: firrtl.int.sizeof %clk
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%size = firrtl.int.generic "circt.sizeof" %clk : (!firrtl.clock) -> !firrtl.uint<32>
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firrtl.matchingconnect %s, %size : !firrtl.uint<32>
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// CHECK: firrtl.int.isX
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%isX = firrtl.int.generic "circt.isX" %clk : (!firrtl.clock) -> !firrtl.uint<1>
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firrtl.matchingconnect %io1, %isX : !firrtl.uint<1>
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// CHECK: firrtl.int.plusargs.test "foo"
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%foo = firrtl.int.generic "circt.plusargs.test" <FORMAT: none = "foo"> : () -> !firrtl.uint<1>
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firrtl.matchingconnect %io2, %foo : !firrtl.uint<1>
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// CHECK: firrtl.int.plusargs.value "foo" : !firrtl.uint<5>
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%pav = firrtl.int.generic "circt.plusargs.value" <FORMAT: none = "foo"> : () -> !firrtl.bundle<found: uint<1>, result: uint<5>>
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%found = firrtl.subfield %pav[found] : !firrtl.bundle<found: uint<1>, result: uint<5>>
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%result = firrtl.subfield %pav[result] : !firrtl.bundle<found: uint<1>, result: uint<5>>
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firrtl.matchingconnect %io3, %found : !firrtl.uint<1>
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firrtl.matchingconnect %io4, %result : !firrtl.uint<5>
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}
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// CHECK-LABEL: @ClockGate
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firrtl.module @ClockGate(in %clk: !firrtl.clock, in %en: !firrtl.uint<1>) {
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// CHECK-NEXT: firrtl.int.clock_gate %clk, %en
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firrtl.int.generic "circt.clock_gate" %clk, %en : (!firrtl.clock, !firrtl.uint<1>) -> !firrtl.clock
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// CHECK-NEXT: firrtl.int.clock_gate %clk, %en, %en
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firrtl.int.generic "circt.clock_gate" %clk, %en, %en : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.clock
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}
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// CHECK-LABEL: @ClockInverter
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firrtl.module @ClockInverter(in %clk: !firrtl.clock) {
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// CHECK-NEXT: firrtl.int.clock_inv %clk
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firrtl.int.generic "circt.clock_inv" %clk : (!firrtl.clock) -> !firrtl.clock
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}
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// CHECK-LABEL: @ClockDivider
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firrtl.module @ClockDivider(in %clk: !firrtl.clock) {
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// CHECK-NEXT: firrtl.int.clock_div %clk by 8
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firrtl.int.generic "circt.clock_div" <POW_2: i8 = 8> %clk : (!firrtl.clock) -> !firrtl.clock
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}
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// CHECK-LABEL: firrtl.module @LTL(
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firrtl.module @LTL(in %in0 : !firrtl.uint<1>, in %in1 : !firrtl.uint<1>, in %clk : !firrtl.clock) {
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// CHECK-NEXT: firrtl.int.ltl.and %in0, %in1 :
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firrtl.int.generic "circt_ltl_and" %in0, %in1: (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.or %in0, %in1 :
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firrtl.int.generic "circt_ltl_or" %in0, %in1 : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.intersect %in0, %in1 :
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firrtl.int.generic "circt_ltl_intersect" %in0, %in1 : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.delay %in0, 42 :
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firrtl.int.generic "circt_ltl_delay" <delay: i64 = 42> %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.delay %in0, 42, 1337 :
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firrtl.int.generic "circt_ltl_delay" <delay: i64 = 42, length: i64 = 1337> %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.repeat %in0, 42 :
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firrtl.int.generic "circt_ltl_repeat" <base: i64 = 42> %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.repeat %in0, 42, 1337 :
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firrtl.int.generic "circt_ltl_repeat" <base: i64 = 42, more: i64 = 1337> %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.goto_repeat %in0, 42, 1337 :
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firrtl.int.generic "circt_ltl_goto_repeat" <base: i64 = 42, more: i64 = 1337> %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.non_consecutive_repeat %in0, 42, 1337 :
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firrtl.int.generic "circt_ltl_non_consecutive_repeat" <base: i64 = 42, more: i64 = 1337> %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.concat %in0, %in1 :
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firrtl.int.generic "circt_ltl_concat" %in0, %in1: (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.not %in0 :
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firrtl.int.generic "circt_ltl_not" %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.implication %in0, %in1 :
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firrtl.int.generic "circt_ltl_implication" %in0, %in1 : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.until %in0, %in1 :
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firrtl.int.generic "circt_ltl_until" %in0, %in1 : (!firrtl.uint<1>, !firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.eventually %in0 :
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firrtl.int.generic "circt_ltl_eventually" %in0 : (!firrtl.uint<1>) -> !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.ltl.clock %in0, %clk :
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firrtl.int.generic "circt_ltl_clock" %in0, %clk : (!firrtl.uint<1>, !firrtl.clock) -> !firrtl.uint<1>
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}
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// CHECK-LABEL: firrtl.module @Verif(
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firrtl.module @Verif(in %in : !firrtl.uint<1>) {
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// CHECK-NEXT: firrtl.int.verif.assert %in :
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// CHECK-NEXT: firrtl.int.verif.assert %in {label = "hello"} :
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// CHECK-NEXT: firrtl.int.verif.assume %in :
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// CHECK-NEXT: firrtl.int.verif.cover %in :
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firrtl.int.generic "circt_verif_assert" %in : (!firrtl.uint<1>) -> ()
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firrtl.int.generic "circt_verif_assert" <label: none = "hello"> %in : (!firrtl.uint<1>) -> ()
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firrtl.int.generic "circt_verif_assume" %in : (!firrtl.uint<1>) -> ()
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firrtl.int.generic "circt_verif_cover" %in : (!firrtl.uint<1>) -> ()
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}
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// CHECK-LABEL: firrtl.module private @MuxCell(
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firrtl.module private @MuxCell(in %sel : !firrtl.uint<1>,
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in %sel2 : !firrtl.uint<2>,
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in %d1 : !firrtl.uint,
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in %d2 : !firrtl.uint,
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in %d3 : !firrtl.uint,
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in %d4 : !firrtl.uint) {
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// CHECK-NEXT: firrtl.int.mux2cell(%sel, %d1, %d2)
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// CHECK-NEXT: firrtl.int.mux4cell(%sel2, %d1, %d2, %d3, %d4)
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firrtl.int.generic "circt_mux2cell" %sel, %d1, %d2 : (!firrtl.uint<1>, !firrtl.uint, !firrtl.uint) -> !firrtl.uint
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firrtl.int.generic "circt_mux4cell" %sel2, %d1, %d2, %d3, %d4 : (!firrtl.uint<2>, !firrtl.uint, !firrtl.uint, !firrtl.uint, !firrtl.uint) -> !firrtl.uint
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}
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// CHECK-LABEL: @HasBeenReset
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firrtl.module @HasBeenReset(in %clock: !firrtl.clock, in %reset1: !firrtl.uint<1>, in %reset2: !firrtl.asyncreset, in %reset3: !firrtl.reset) {
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// CHECK-NEXT: firrtl.int.has_been_reset %clock, %reset1 : !firrtl.uint<1>
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// CHECK-NEXT: firrtl.int.has_been_reset %clock, %reset2 : !firrtl.asyncreset
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// CHECK-NEXT: firrtl.int.has_been_reset %clock, %reset3 : !firrtl.reset
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firrtl.int.generic "circt_has_been_reset" %clock, %reset1 : (!firrtl.clock, !firrtl.uint<1>) -> !firrtl.uint<1>
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firrtl.int.generic "circt_has_been_reset" %clock, %reset2 : (!firrtl.clock, !firrtl.asyncreset) -> !firrtl.uint<1>
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firrtl.int.generic "circt_has_been_reset" %clock, %reset3 : (!firrtl.clock, !firrtl.reset) -> !firrtl.uint<1>
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}
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// CHECK-LABEL: firrtl.module @ChiselVerif(
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firrtl.module @ChiselVerif(in %clock: !firrtl.clock,
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in %cond: !firrtl.uint<1>,
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in %enable: !firrtl.uint<1>) {
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// CHECK: firrtl.assert %{{.+}}, %{{.+}}, %{{.+}}, "testing" :
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// CHECK-SAME: isConcurrent = true
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firrtl.int.generic "circt_chisel_assert" <format: none = "testing"> %clock, %cond, %enable : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>) -> ()
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// CHECK: firrtl.assert %{{.+}}, %{{.+}}, %{{.+}}, "message: %d"(
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// CHECK-SAME: guards = ["MACRO_GUARD", "ASDF"]
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// CHECK-SAME: isConcurrent = true
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// CHECK-SAME: name = "label for assert with format string"
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firrtl.int.generic "circt_chisel_assert" <format: none = "message: %d", label: none = "label for assert with format string", guards: none = "MACRO_GUARD;ASDF"> %clock, %cond, %enable, %cond : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>, !firrtl.uint<1>) -> ()
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// CHECK: firrtl.assert %{{.+}}, %{{.+}}, %{{.+}}, "ief: %d"(
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// CHECK-SAME: format = "ifElseFatal"
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// CHECK-SAME: guards = ["MACRO_GUARD", "ASDF"]
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// CHECK-SAME: isConcurrent = true
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// CHECK-SAME: name = "label for ifelsefatal assert"
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firrtl.int.generic "circt_chisel_ifelsefatal" <format: none = "ief: %d", label: none = "label for ifelsefatal assert", guards: none = "MACRO_GUARD;ASDF"> %clock, %cond, %enable, %enable : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>, !firrtl.uint<1>) -> ()
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// CHECK: firrtl.assume %{{.+}}, %{{.+}}, %{{.+}}, "text: %d"(
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// CHECK-SAME: isConcurrent = true
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// CHECK-SAME: name = "label for assume"
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firrtl.int.generic "circt_chisel_assume" <format: none = "text: %d", label: none = "label for assume"> %clock, %cond, %enable, %enable : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>, !firrtl.uint<1>) -> ()
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// CHECK: firrtl.cover %{{.+}}, %{{.+}}, %{{.+}}, "" :
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// CHECK-SAME: isConcurrent = true
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// CHECK-SAME: name = "label for cover"
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firrtl.int.generic "circt_chisel_cover" <label: none = "label for cover"> %clock, %cond, %enable : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>) -> ()
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// CHECK: firrtl.int.unclocked_assume %{{.+}}, %{{.+}}, "text: %d"(
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// CHECK-SAME: guards = ["MACRO_GUARD", "ASDF"]
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// CHECK-SAME: name = "label for unr"
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firrtl.int.generic "circt.unclocked_assume" <format: none = "text: %d", label: none = "label for unr", guards: none = "MACRO_GUARD;ASDF"> %cond, %enable, %enable : (!firrtl.uint<1>, !firrtl.uint<1>, !firrtl.uint<1>) -> ()
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}
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// CHECK-LABEL: firrtl.module private @ProbeIntrinsicTest
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firrtl.module private @ProbeIntrinsicTest(in %clock : !firrtl.clock, in %data : !firrtl.uint<32>) {
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// CHECK-NEXT: firrtl.int.fpga_probe %clock, %data : !firrtl.uint<32>
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firrtl.int.generic "circt_fpga_probe" %data, %clock : (!firrtl.uint<32>, !firrtl.clock) -> ()
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}
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// CHECK-LABEL: firrtl.module private @DPIIntrinsicTest
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firrtl.module private @DPIIntrinsicTest(in %clock : !firrtl.clock, in %enable : !firrtl.uint<1>, in %in1: !firrtl.uint<8>, in %in2: !firrtl.uint<8>) {
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// CHECK-NEXT: %0 = firrtl.int.dpi.call "clocked_result"(%in1, %in2) clock %clock enable %enable {inputNames = ["foo", "bar"], outputName = "baz"} : (!firrtl.uint<8>, !firrtl.uint<8>) -> !firrtl.uint<8>
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%0 = firrtl.int.generic "circt_dpi_call" <isClocked: ui32 = 1, functionName: none = "clocked_result", inputNames: none = "foo;bar", outputName: none = "baz"> %clock, %enable, %in1, %in2 : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<8>, !firrtl.uint<8>) -> !firrtl.uint<8>
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// CHECK-NEXT: firrtl.int.dpi.call "clocked_void"(%in1, %in2) clock %clock enable %enable : (!firrtl.uint<8>, !firrtl.uint<8>) -> ()
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firrtl.int.generic "circt_dpi_call" <isClocked: ui32 = 1, functionName: none = "clocked_void"> %clock, %enable, %in1, %in2 : (!firrtl.clock, !firrtl.uint<1>, !firrtl.uint<8>, !firrtl.uint<8>) -> ()
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// CHECK-NEXT: %1 = firrtl.int.dpi.call "unclocked_result"(%in1, %in2) enable %enable : (!firrtl.uint<8>, !firrtl.uint<8>) -> !firrtl.uint<8>
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%1 = firrtl.int.generic "circt_dpi_call" <isClocked: ui32 = 0, functionName: none = "unclocked_result"> %enable, %in1, %in2 : (!firrtl.uint<1>, !firrtl.uint<8>, !firrtl.uint<8>) -> !firrtl.uint<8>
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}
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}
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