mirror of https://github.com/llvm/circt.git
33 lines
1.2 KiB
MLIR
33 lines
1.2 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl.module(firrtl-lower-intrinsics)))' -verify-diagnostics --split-input-file %s
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firrtl.circuit "UnknownIntrinsic" {
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firrtl.module @UnknownIntrinsic(in %data: !firrtl.uint<32>) {
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%0 = firrtl.wire : !firrtl.uint<32>
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// expected-error @below {{unknown intrinsic}}
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// expected-error @below {{failed to legalize}}
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firrtl.int.generic "unknown_intrinsic" %0 : (!firrtl.uint<32>) -> ()
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firrtl.matchingconnect %0, %data : !firrtl.uint<32>
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}
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}
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// -----
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firrtl.circuit "InvalidCGOperand" {
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firrtl.module @InvalidCGOperand(in %clk: !firrtl.clock, in %en: !firrtl.uint<2>) {
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// expected-error @below {{circt.clock_gate input 1 not size 1}}
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// expected-error @below {{failed to legalize}}
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%0 = firrtl.int.generic "circt.clock_gate" %clk, %en : (!firrtl.clock, !firrtl.uint<2>) -> !firrtl.clock
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}
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}
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// -----
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firrtl.circuit "MissingParam" {
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firrtl.module @MissingParam(in %clk: !firrtl.clock, in %en: !firrtl.uint<2>) {
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// expected-error @below {{circt_plusargs_test is missing parameter FORMAT}}
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// expected-error @below {{failed to legalize}}
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%0 = firrtl.int.generic "circt_plusargs_test" : () -> !firrtl.uint<1>
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}
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}
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