mirror of https://github.com/llvm/circt.git
83 lines
3.8 KiB
MLIR
83 lines
3.8 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl.module(firrtl-lint)))' --verify-diagnostics --split-input-file %s | FileCheck %s
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firrtl.circuit "lint_tests" {
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// CHECK: firrtl.module @lint_tests
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firrtl.module @lint_tests(in %en: !firrtl.uint<1>, in %pred: !firrtl.uint<1>, in %reset: !firrtl.reset, in %clock: !firrtl.clock) {
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%0 = firrtl.asUInt %reset : (!firrtl.reset) -> !firrtl.uint<1>
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// CHECK: firrtl.assert
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firrtl.assert %clock, %pred, %en, "valid" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1> {eventControl = 0 : i32, isConcurrent = false}
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// CHECK: firrtl.assert
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firrtl.assert %clock, %0, %en, "valid" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1> {eventControl = 0 : i32, isConcurrent = false}
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%false = firrtl.constant 0 : !firrtl.uint<1>
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// CHECK: firrtl.assert
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firrtl.assert %clock, %false, %en, "valid" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1> {eventControl = 0 : i32, isConcurrent = false}
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// CHECK: firrtl.int.verif.assert
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firrtl.int.verif.assert %pred : !firrtl.uint<1>
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// CHECK: firrtl.int.verif.assert
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firrtl.when %en : !firrtl.uint<1> {
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firrtl.int.verif.assert %false : !firrtl.uint<1>
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}
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}
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}
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// -----
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firrtl.circuit "assert_const" {
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firrtl.module @assert_const(in %clock: !firrtl.clock) {
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%true = firrtl.constant 1 : !firrtl.uint<1>
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// expected-note @below {{constant defined here}}
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%false = firrtl.constant 0 : !firrtl.uint<1>
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// expected-error @below {{'firrtl.assert' op is guaranteed to fail simulation, as the predicate is constant false}}
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firrtl.assert %clock, %false, %true, "valid" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1> {eventControl = 0 : i32, isConcurrent = false}
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}
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}
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// -----
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firrtl.circuit "assert_reset" {
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// expected-note @below {{reset signal defined here}}
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firrtl.module @assert_reset(in %en: !firrtl.uint<1>, in %pred: !firrtl.uint<1>, in %reset: !firrtl.reset, in %reset_async: !firrtl.asyncreset, in %clock: !firrtl.clock) {
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%0 = firrtl.asUInt %reset : (!firrtl.reset) -> !firrtl.uint<1>
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%true = firrtl.constant 1 : !firrtl.uint<1>
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%false = firrtl.constant 0 : !firrtl.uint<1>
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// expected-error @below {{op is guaranteed to fail simulation, as the predicate is a reset signal}}
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firrtl.assert %clock, %0, %true, "valid" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1> {eventControl = 0 : i32, isConcurrent = false}
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}
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}
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// -----
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firrtl.circuit "assert_const2" {
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firrtl.module @assert_const2() {
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// expected-note @below {{constant defined here}}
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%false = firrtl.constant 0 : !firrtl.uint<1>
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// expected-error @below {{op is guaranteed to fail simulation, as the predicate is constant false}}
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firrtl.int.verif.assert %false : !firrtl.uint<1>
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}
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}
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// -----
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firrtl.circuit "assert_reset2" {
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// expected-note @below {{reset signal defined here}}
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firrtl.module @assert_reset2(in %en: !firrtl.uint<1>, in %pred: !firrtl.uint<1>, in %reset: !firrtl.reset, in %reset_async: !firrtl.asyncreset, in %clock: !firrtl.clock) {
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%0 = firrtl.asUInt %reset : (!firrtl.reset) -> !firrtl.uint<1>
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// expected-error @below {{op is guaranteed to fail simulation, as the predicate is a reset signal}}
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firrtl.int.verif.assert %0 : !firrtl.uint<1>
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}
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}
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// -----
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firrtl.circuit "assert_reset3" {
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firrtl.layer @GroupFoo bind {}
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// expected-note @below {{reset signal defined here}}
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firrtl.module @assert_reset3(in %en: !firrtl.uint<1>, in %pred: !firrtl.uint<1>, in %reset: !firrtl.reset, in %reset_async: !firrtl.asyncreset, in %clock: !firrtl.clock) {
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%0 = firrtl.asUInt %reset : (!firrtl.reset) -> !firrtl.uint<1>
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firrtl.layerblock @GroupFoo {
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// expected-error @below {{op is guaranteed to fail simulation, as the predicate is a reset signal}}
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firrtl.int.verif.assert %0 : !firrtl.uint<1>
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}
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}
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}
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