mirror of https://github.com/llvm/circt.git
124 lines
3.8 KiB
MLIR
124 lines
3.8 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl-lower-annotations))' -split-input-file %s -verify-diagnostics
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// Every Wiring pin must have exactly one defined source
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//
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// expected-error @+1 {{Unable to resolve source for pin: "foo_out"}}
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firrtl.circuit "Foo" attributes {
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rawAnnotations = [
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{
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class = "firrtl.passes.wiring.SinkAnnotation",
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target = "Foo.Foo.out",
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pin = "foo_out"
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}]} {
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firrtl.module @Foo(out %out: !firrtl.uint<1>) {
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firrtl.skip
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}
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}
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// -----
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// Every Wiring pin must have at least one defined sink
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//
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// expected-error @+1 {{Unable to resolve sink(s) for pin: "foo_in"}}
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firrtl.circuit "Foo" attributes {
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rawAnnotations = [
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{
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class = "firrtl.passes.wiring.SourceAnnotation",
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target = "Foo.Foo.in",
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pin = "foo_in"
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}]} {
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firrtl.module @Foo(in %in: !firrtl.uint<1>) {
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firrtl.skip
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}
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}
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// -----
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// Multiple SourceAnnotations for the same pin are forbidden
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//
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// expected-error @+2 {{Unable to apply annotation: {class = "firrtl.passes.wiring.SourceAnnotation", pin = "foo_out", target = "Foo.Foo.b"}}}
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// expected-error @+1 {{More than one firrtl.passes.wiring.SourceAnnotation defined for pin "foo_out"}}
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firrtl.circuit "Foo" attributes {
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rawAnnotations = [
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{
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class = "firrtl.passes.wiring.SinkAnnotation",
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target = "Foo.Foo.out",
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pin = "foo_out"
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},
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{
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class = "firrtl.passes.wiring.SourceAnnotation",
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target = "Foo.Foo.a",
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pin = "foo_out"
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},
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{
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class = "firrtl.passes.wiring.SourceAnnotation",
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target = "Foo.Foo.b",
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pin = "foo_out"
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}]} {
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firrtl.module @Foo(in %a: !firrtl.uint<1>, in %b: !firrtl.uint<1>, out %out: !firrtl.uint<1>) {
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firrtl.skip
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}
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}
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// -----
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// Error if attempt to wire incompatible types.
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firrtl.circuit "Foo" attributes {
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rawAnnotations = [
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{
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class = "firrtl.passes.wiring.SourceAnnotation",
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target = "~Foo|Bar>y",
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pin = "xyz"
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},
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{
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class = "firrtl.passes.wiring.SinkAnnotation",
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target = "~Foo|Foo>x",
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pin = "xyz"
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}
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]} {
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firrtl.module private @Bar() {
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// expected-error @below {{Wiring Problem source type '!firrtl.bundle<a: uint<1>, b: uint<2>>' does not match sink type '!firrtl.uint<1>'}}
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%y = firrtl.wire interesting_name : !firrtl.bundle<a: uint<1>, b: uint<2>>
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%invalid_reset = firrtl.invalidvalue : !firrtl.bundle<a: uint<1>, b: uint<2>>
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firrtl.matchingconnect %y, %invalid_reset : !firrtl.bundle<a: uint<1>, b: uint<2>>
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}
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firrtl.module @Foo() {
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firrtl.instance bar interesting_name @Bar()
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// expected-note @below {{The sink is here.}}
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%x = firrtl.wire interesting_name : !firrtl.uint<1>
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%invalid_ui1 = firrtl.invalidvalue : !firrtl.uint<1>
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firrtl.matchingconnect %x, %invalid_ui1 : !firrtl.uint<1>
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}
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}
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// -----
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// Error on wiring through public
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firrtl.circuit "FooBar" attributes {
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rawAnnotations = [
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{
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class = "firrtl.passes.wiring.SinkAnnotation",
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target = "FooBar.Foo.out",
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pin = "foo_out"
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},
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{
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class = "firrtl.passes.wiring.SourceAnnotation",
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target = "FooBar.FooBar.io.in",
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pin = "foo_out"
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}]} {
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// expected-note @below {{sink here}}
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firrtl.module private @Foo(out %out: !firrtl.uint<1>) {
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}
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// expected-error @below {{cannot wire port through this public module}}
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firrtl.module public @Bar(out %out: !firrtl.uint<1>) {
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%foo_out = firrtl.instance foo interesting_name @Foo(out out: !firrtl.uint<1>)
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firrtl.matchingconnect %out, %foo_out : !firrtl.uint<1>
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}
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// expected-note @below {{source here}}
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firrtl.module @FooBar(out %io: !firrtl.bundle<in flip: uint<1>, out: uint<1>>) {
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%0 = firrtl.subfield %io[out] : !firrtl.bundle<in flip: uint<1>, out: uint<1>>
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%bar_out = firrtl.instance bar interesting_name @Bar(out out: !firrtl.uint<1>)
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firrtl.matchingconnect %0, %bar_out : !firrtl.uint<1>
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}
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}
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