mirror of https://github.com/llvm/circt.git
75 lines
2.6 KiB
MLIR
75 lines
2.6 KiB
MLIR
// RUN: circt-opt -pass-pipeline='builtin.module(firrtl-inner-symbol-dce)' %s | FileCheck %s
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// CHECK-LABEL: firrtl.circuit "Simple"
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firrtl.circuit "Simple" attributes {
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annotations = [
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{
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class = "circuit",
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key = #hw.innerNameRef<@Simple::@w0>,
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dict = {key = #hw.innerNameRef<@Simple::@w1>},
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array = [#hw.innerNameRef<@Simple::@w2>],
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payload = "hello"
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}
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]} {
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// CHECK-LABEL: firrtl.module @Simple
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firrtl.module @Simple() {
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// CHECK-NEXT: @w0
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%w0 = firrtl.wire sym @w0 : !firrtl.uint<1>
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// CHECK-NEXT: @w1
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%w1 = firrtl.wire sym @w1 : !firrtl.uint<1>
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// CHECK-NEXT: @w2
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%w2 = firrtl.wire sym @w2 : !firrtl.uint<1>
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// CHECK-NEXT: @w3
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%w3 = firrtl.wire sym @w3 : !firrtl.uint<1>
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// CHECK-NEXT: %w4
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// CHECK-NOT: @w4
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%w4 = firrtl.wire sym @w4 : !firrtl.uint<1>
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%out, %out2, %out3 = firrtl.instance child sym @child @Child(out out: !firrtl.uint<1>, out out2: !firrtl.uint<1>, out out3: !firrtl.vector<uint<1>,2>)
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%eo, %eo2, %eo3 = firrtl.instance child sym @extchild @ExtChild(out out: !firrtl.uint<1>, out out2: !firrtl.uint<1>, out out3: !firrtl.vector<uint<1>,2>)
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}
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// CHECK-LABEL: firrtl.module @Child
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// CHECK-NOT: @deadportsym
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// CHECK-SAME: @outsym2
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// CHECK-SAME: @outsym3
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firrtl.module @Child(
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out %out : !firrtl.uint<1> sym @deadportsym,
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out %out2 : !firrtl.uint<1> sym @outsym2,
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out %out3 : !firrtl.vector<uint<1>,2> sym [<@outsym3,1,public>])
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{
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// CHECK-NEXT: @w5
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%w5 = firrtl.wire sym @w5 : !firrtl.uint<1>
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%c0_ui1 = firrtl.constant 0: !firrtl.uint<1>
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firrtl.matchingconnect %out, %c0_ui1 : !firrtl.uint<1>
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firrtl.matchingconnect %out2, %c0_ui1 : !firrtl.uint<1>
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// CHECK: @x
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// CHECK-NOT: @y
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%wire = firrtl.wire sym [<@x,1,public>,<@y,2,public>] : !firrtl.vector<uint<1>,2>
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firrtl.matchingconnect %out3, %wire : !firrtl.vector<uint<1>,2>
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}
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// CHECK-LABEL: firrtl.extmodule @ExtChild
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// CHECK-NOT: @deadportsym
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// CHECK-SAME: @outsym2
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// CHECK-SAME: @outsym3
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firrtl.extmodule @ExtChild(
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out out : !firrtl.uint<1> sym @deadportsym,
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out out2 : !firrtl.uint<1> sym @outsym2,
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out out3 : !firrtl.vector<uint<1>,2> sym [<@outsym3,1,public>])
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hw.hierpath private @wire [@Simple::@child, @Child::@w5]
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hw.hierpath private @wireField [@Simple::@child, @Child::@x]
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hw.hierpath private @port [@Simple::@child, @Child::@outsym2]
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hw.hierpath private @portField [@Simple::@child, @Child::@outsym3]
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hw.hierpath private @extPort [@Simple::@extchild, @ExtChild::@outsym2]
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hw.hierpath private @extPortField [@Simple::@extchild, @ExtChild::@outsym3]
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}
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sv.verbatim "{{0}}" {symbols = [#hw.innerNameRef<@Simple::@w3>]}
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