mirror of https://github.com/llvm/circt.git
59 lines
3.8 KiB
MLIR
59 lines
3.8 KiB
MLIR
// RUN: circt-opt --firrtl-inject-dut-hier --firrtl-extract-instances --verify-diagnostics %s | FileCheck %s
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// Tests extracted from:
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// - test/scala/firrtl/ExtractClockGates.scala
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//===----------------------------------------------------------------------===//
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// ExtractClockGates Multigrouping
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//===----------------------------------------------------------------------===//
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// CHECK: firrtl.circuit "ExtractClockGatesMultigrouping"
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firrtl.circuit "ExtractClockGatesMultigrouping" attributes {annotations = [{class = "sifive.enterprise.firrtl.ExtractClockGatesFileAnnotation", filename = "ClockGates.txt", group = "ClockGatesGroup"}, {class = "sifive.enterprise.firrtl.InjectDUTHierarchyAnnotation", name = "InjectedSubmodule"}]} {
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firrtl.extmodule private @EICG_wrapper(in in: !firrtl.clock, in en: !firrtl.uint<1>, out out: !firrtl.clock) attributes {defname = "EICG_wrapper"}
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// CHECK-LABEL: firrtl.module private @SomeModule
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firrtl.module private @SomeModule(in %clock: !firrtl.clock, in %en: !firrtl.uint<1>) {
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// CHECK-NOT: firrtl.instance gate @EICG_wrapper
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%gate_in, %gate_en, %gate_out = firrtl.instance gate @EICG_wrapper(in in: !firrtl.clock, in en: !firrtl.uint<1>, out out: !firrtl.clock)
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firrtl.connect %gate_in, %clock : !firrtl.clock, !firrtl.clock
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firrtl.connect %gate_en, %en : !firrtl.uint<1>, !firrtl.uint<1>
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}
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// CHECK-LABEL: firrtl.module private @InjectedSubmodule
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// CHECK: firrtl.instance inst0 sym [[INST0_SYM:@.+]] @SomeModule
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// CHECK: firrtl.instance inst1 sym [[INST1_SYM:@.+]] @SomeModule
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// CHECK-LABEL: firrtl.module private @ClockGatesGroup
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// CHECK: firrtl.instance gate sym @sym @EICG_wrapper
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// CHECK: firrtl.instance gate sym @sym_0 @EICG_wrapper
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// CHECK-LABEL: firrtl.module private @DUTModule
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firrtl.module private @DUTModule(in %clock: !firrtl.clock, in %foo_en: !firrtl.uint<1>, in %bar_en: !firrtl.uint<1>) attributes {annotations = [{class = "sifive.enterprise.firrtl.MarkDUTAnnotation"}]} {
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// CHECK-NOT: firrtl.instance gate @EICG_wrapper
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// CHECK-NOT: firrtl.instance gate @EICG_wrapper
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%inst0_clock, %inst0_en = firrtl.instance inst0 @SomeModule(in clock: !firrtl.clock, in en: !firrtl.uint<1>)
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%inst1_clock, %inst1_en = firrtl.instance inst1 @SomeModule(in clock: !firrtl.clock, in en: !firrtl.uint<1>)
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// CHECK: firrtl.instance ClockGatesGroup sym [[CLKGRP_SYM:@.+]] @ClockGatesGroup
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// CHECK: firrtl.instance InjectedSubmodule sym [[INJMOD_SYM:@.+]] @InjectedSubmodule
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firrtl.connect %inst0_clock, %clock : !firrtl.clock, !firrtl.clock
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firrtl.connect %inst1_clock, %clock : !firrtl.clock, !firrtl.clock
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firrtl.connect %inst0_en, %foo_en : !firrtl.uint<1>, !firrtl.uint<1>
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firrtl.connect %inst1_en, %bar_en : !firrtl.uint<1>, !firrtl.uint<1>
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}
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// CHECK-LABEL: firrtl.module @ExtractClockGatesMultigrouping
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firrtl.module @ExtractClockGatesMultigrouping(in %clock: !firrtl.clock, in %foo_en: !firrtl.uint<1>, in %bar_en: !firrtl.uint<1>) {
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%dut_clock, %dut_foo_en, %dut_bar_en = firrtl.instance dut @DUTModule(in clock: !firrtl.clock, in foo_en: !firrtl.uint<1>, in bar_en: !firrtl.uint<1>)
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firrtl.connect %dut_clock, %clock : !firrtl.clock, !firrtl.clock
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firrtl.connect %dut_bar_en, %bar_en : !firrtl.uint<1>, !firrtl.uint<1>
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firrtl.connect %dut_foo_en, %foo_en : !firrtl.uint<1>, !firrtl.uint<1>
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}
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// CHECK: emit.file "ClockGates.txt" {
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// CHECK-NEXT: sv.verbatim
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// CHECK-SAME{LITERAL}: clock_gate_1 -> {{0}}.{{1}}.{{2}}\0A
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// CHECK-SAME{LITERAL}: clock_gate_0 -> {{0}}.{{1}}.{{3}}\0A
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// CHECK-SAME: symbols = [
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// CHECK-SAME: @DUTModule
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// CHECK-SAME: #hw.innerNameRef<@DUTModule::[[INJMOD_SYM]]>
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// CHECK-SAME: #hw.innerNameRef<@InjectedSubmodule::[[INST0_SYM]]>
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// CHECK-SAME: #hw.innerNameRef<@InjectedSubmodule::[[INST1_SYM]]>
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// CHECK-SAME: ]
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}
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