mirror of https://github.com/llvm/circt.git
253 lines
8.2 KiB
MLIR
253 lines
8.2 KiB
MLIR
// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(any(firrtl-expand-whens)))' -verify-diagnostics --split-input-file %s
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// This test is checking each kind of declaration to ensure that it is caught
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// by the initialization coverage check. This is also testing that we can emit
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// all errors in a module at once.
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization(in %clock : !firrtl.clock, in %en : !firrtl.uint<1>, in %p : !firrtl.uint<1>, in %in0 : !firrtl.bundle<a flip: uint<1>>, out %out0 : !firrtl.uint<2>, out %out1 : !firrtl.bundle<a flip: uint<1>>) {
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// expected-error @above {{port "in0.a" not fully initialized in "CheckInitialization"}}
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// expected-error @above {{port "out0" not fully initialized in "CheckInitialization"}}
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization() {
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// expected-error @below {{sink "w.a" not fully initialized in "CheckInitialization"}}
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// expected-error @below {{sink "w.b" not fully initialized in "CheckInitialization"}}
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%w = firrtl.wire : !firrtl.bundle<a : uint<1>, b flip: uint<1>>
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @simple(in %in : !firrtl.uint<1>, out %out : !firrtl.uint<1>) {
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firrtl.connect %out, %in : !firrtl.uint<1>, !firrtl.uint<1>
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}
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firrtl.module @CheckInitialization() {
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// expected-error @below {{sink "test.in" not fully initialized}}
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%simple_out, %simple_in = firrtl.instance test @simple(in in : !firrtl.uint<1>, out out : !firrtl.uint<1>)
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization() {
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// expected-error @below {{sink "memory.r.addr" not fully initialized}}
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// expected-error @below {{sink "memory.r.en" not fully initialized}}
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// expected-error @below {{sink "memory.r.clk" not fully initialized}}
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%memory_r = firrtl.mem Undefined {depth = 16 : i64, name = "memory", portNames = ["r"], readLatency = 0 : i32, writeLatency = 1 : i32} : !firrtl.bundle<addr: uint<4>, en: uint<1>, clk: clock, data flip: bundle<a: uint<8>, b: uint<8>>>
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}
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}
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// -----
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firrtl.circuit "declaration_in_when" {
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// Check that wires declared inside of a when are detected as uninitialized.
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firrtl.module @declaration_in_when(in %p : !firrtl.uint<1>) {
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firrtl.when %p : !firrtl.uint<1> {
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// expected-error @below {{sink "w_then" not fully initialized}}
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%w_then = firrtl.wire : !firrtl.uint<2>
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}
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}
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}
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// -----
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firrtl.circuit "declaration_in_when" {
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// Check that wires declared inside of a when are detected as uninitialized.
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firrtl.module @declaration_in_when(in %p : !firrtl.uint<1>) {
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firrtl.when %p : !firrtl.uint<1> {
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} else {
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// expected-error @below {{sink "w_else" not fully initialized}}
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%w_else = firrtl.wire : !firrtl.uint<2>
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}
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}
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}
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// -----
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firrtl.circuit "complex" {
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// Test that a wire set across separate when statements is detected as not
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// completely initialized.
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firrtl.module @complex(in %p : !firrtl.uint<1>, in %q : !firrtl.uint<1>) {
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// expected-error @below {{sink "w" not fully initialized}}
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%w = firrtl.wire : !firrtl.uint<2>
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firrtl.when %p : !firrtl.uint<1> {
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%c1_ui2 = firrtl.constant 1 : !firrtl.uint<2>
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firrtl.connect %w, %c1_ui2 : !firrtl.uint<2>, !firrtl.uint<2>
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}
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firrtl.when %q : !firrtl.uint<1> {
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} else {
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%c1_ui2 = firrtl.constant 1 : !firrtl.uint<2>
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firrtl.connect %w, %c1_ui2 : !firrtl.uint<2>, !firrtl.uint<2>
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}
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization(out %out : !firrtl.vector<uint<1>, 1>) {
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// expected-error @above {{port "out[0]" not fully initialized in "CheckInitialization"}}
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization() {
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// expected-error @below {{sink "w[0]" not fully initialized}}
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// expected-error @below {{sink "w[1]" not fully initialized}}
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%w = firrtl.wire : !firrtl.vector<uint<1>, 2>
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization(in %in : !firrtl.uint<1>, out %out : !firrtl.vector<uint<1>, 2>) {
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// expected-error @above {{port "out[1]" not fully initialized in "CheckInitialization"}}
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%0 = firrtl.subindex %out[0] : !firrtl.vector<uint<1>, 2>
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firrtl.connect %0, %in : !firrtl.uint<1>, !firrtl.uint<1>
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization(in %in : !firrtl.uint<1>, out %out : !firrtl.vector<vector<uint<1>, 1>, 1>) {
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// expected-error @above {{port "out[0][0]" not fully initialized in "CheckInitialization"}}
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}
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}
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// -----
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firrtl.circuit "CheckInitialization" {
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firrtl.module @CheckInitialization(in %p : !firrtl.uint<1>, out %out: !firrtl.vector<bundle<a:uint<1>, b:uint<1>>, 1>) {
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// expected-error @above {{port "out[0].a" not fully initialized in "CheckInitialization"}}
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// expected-error @above {{port "out[0].b" not fully initialized in "CheckInitialization"}}
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}
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}
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// -----
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// Check initialization error is produced for out-references
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firrtl.circuit "RefInitOut" {
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firrtl.module @RefInitOut(out %out : !firrtl.probe<uint<1>>) {
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// expected-error @above {{port "out" not fully initialized in "RefInitOut"}}
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}
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}
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// -----
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// Check initialization error is produced for output property ports on modules.
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firrtl.circuit "PropInitOut" {
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firrtl.module @PropInitOut(out %out : !firrtl.string) {
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// expected-error @above {{port "out" not fully initialized in "PropInitOut"}}
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}
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}
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// -----
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// Check initialization error is produced for output property ports on classes.
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firrtl.circuit "PropInitOut" {
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// expected-error @below {{port "out" not fully initialized in "Class"}}
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firrtl.class @Class(out %out: !firrtl.string) {}
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firrtl.module @PropInitOut() {}
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}
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// -----
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// Check initialization error is produced for input property ports on instances.
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firrtl.circuit "PropInitIn" {
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firrtl.module @Child(in %in: !firrtl.string) {}
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firrtl.module @PropInitIn() {
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%child_in = firrtl.instance child @Child(in in : !firrtl.string)
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// expected-error @above {{sink "child.in" not fully initialized in "PropInitIn"}}
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}
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}
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// -----
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// Check initialization error is produced for input property ports on local objects.
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firrtl.circuit "PropInitIn" {
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firrtl.class @Class(in %in: !firrtl.string) {}
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firrtl.module @PropInitIn() {
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// expected-error @below {{sink "obj.in" not fully initialized in "PropInitIn"}}
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%obj = firrtl.object @Class(in in : !firrtl.string)
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}
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}
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// -----
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// Check initialization error is produced for output object ports on modules.
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firrtl.circuit "Test" {
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firrtl.class @Class() {}
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// expected-error @below {{port "out" not fully initialized in "Test"}}
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firrtl.module @Test(out %out: !firrtl.class<@Class()>) {}
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}
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// -----
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// Check initialization error is produced for output object ports on classes.
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firrtl.circuit "Test" {
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firrtl.class @Class1() {}
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// expected-error @below {{port "out" not fully initialized in "Class2"}}
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firrtl.class @Class2(out %out: !firrtl.class<@Class1()>) {}
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firrtl.module @Test() {}
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}
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// -----
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// Check initialization error is produced for input object ports on instances.
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firrtl.circuit "Test" {
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firrtl.class @Class() {}
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firrtl.module @Module(in %in: !firrtl.class<@Class()>) {}
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firrtl.module @Test() {
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// expected-error @below {{sink "mod.in" not fully initialized in "Test"}}
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%mod_in = firrtl.instance mod @Module(in in : !firrtl.class<@Class()>)
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}
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}
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// -----
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// Check initialization error is produced for input object ports on local objects.
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firrtl.circuit "Test" {
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firrtl.class @Class1() { }
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firrtl.class @Class2(in %in: !firrtl.class<@Class1()>) {}
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firrtl.module @Test() {
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// expected-error @below {{sink "obj.in" not fully initialized in "Test"}}
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%obj = firrtl.object @Class2(in in : !firrtl.class<@Class1()>)
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}
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}
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// -----
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// Check initialization errors for local objects are produced under firrtl classes.
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firrtl.circuit "Test" {
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firrtl.class @Class1(in %in: !firrtl.string) {}
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firrtl.class @Class2() {
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// expected-error @below {{sink "obj.in" not fully initialized in "Class2"}}
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%obj = firrtl.object @Class1(in in: !firrtl.string)
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}
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firrtl.module @Test() {}
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}
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// -----
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// Check initialization errors for objects in wires are produced.
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firrtl.circuit "Test" {
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firrtl.class @Class(in %in: !firrtl.string) {}
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firrtl.module @Test() {
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// expected-error @below {{sink "w" not fully initialized in "Test"}}
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%w = firrtl.wire : !firrtl.class<@Class()>
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}
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}
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