mirror of https://github.com/llvm/circt.git
27 lines
976 B
MLIR
27 lines
976 B
MLIR
// RUN: circt-opt -firrtl-lower-annotations -mlir-print-op-generic -split-input-file %s | FileCheck %s
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// A ReferenceTarget/ComponentName pointing at a module/extmodule port should
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// work.
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firrtl.circuit "Foo" attributes {rawAnnotations = [
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{class = "circt.test", data = "a", target = "~Foo|Bar>bar"},
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{class = "circt.test", data = "b", target = "Foo.Foo.foo"}
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]} {
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firrtl.extmodule @Bar(in bar: !firrtl.uint<1>)
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firrtl.module @Foo(in %foo: !firrtl.uint<1>) {
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%bar_bar = firrtl.instance bar @Bar(in bar: !firrtl.uint<1>)
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firrtl.matchingconnect %bar_bar, %foo : !firrtl.uint<1>
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}
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}
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// CHECK-LABEL: "firrtl.extmodule"() <
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// CHECK-SAME: portAnnotations = {{['[']['[']}}{class = "circt.test", data = "a"}]]
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// CHECK-SAME: sym_name = "Bar"
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// CHECK-SAME: > ({
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// CHECK: })
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// CHECK-LABEL: "firrtl.module"() <
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// CHECK-SAME: portAnnotations = {{['[']['[']}}{class = "circt.test", data = "b"}]]
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// CHECK-SAME: sym_name = "Foo"
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// CHECK-SAME: > ({
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// CHECK: })
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